Lines Matching refs:Binop
1189 switch (e->Iex.Binop.op) {
1207 HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1);
1213 e->Iex.Binop.arg2);
1217 e->Iex.Binop.arg2);
1227 switch (e->Iex.Binop.op) {
1240 HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1);
1246 ri_srcR = iselWordExpr_RH5u(env, e->Iex.Binop.arg2);
1248 ri_srcR = iselWordExpr_RH6u(env, e->Iex.Binop.arg2);
1283 if (e->Iex.Binop.op == Iop_DivS32 ||
1284 e->Iex.Binop.op == Iop_DivU32) {
1285 Bool syned = toBool(e->Iex.Binop.op == Iop_DivS32);
1287 HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1);
1288 HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2);
1293 if (e->Iex.Binop.op == Iop_DivS64 ||
1294 e->Iex.Binop.op == Iop_DivU64) {
1295 Bool syned = toBool(e->Iex.Binop.op == Iop_DivS64);
1297 HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1);
1298 HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2);
1306 if (e->Iex.Binop.op == Iop_Mul32
1307 || e->Iex.Binop.op == Iop_Mul64) {
1309 Bool sz32 = (e->Iex.Binop.op != Iop_Mul64);
1311 HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1);
1312 HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2);
1320 && (e->Iex.Binop.op == Iop_MullU32
1321 || e->Iex.Binop.op == Iop_MullS32)) {
1325 Bool syned = toBool(e->Iex.Binop.op == Iop_MullS32);
1326 HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1);
1327 HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2);
1342 if (e->Iex.Binop.op == Iop_CmpORD32S
1343 || e->Iex.Binop.op == Iop_CmpORD32U) {
1344 Bool syned = toBool(e->Iex.Binop.op == Iop_CmpORD32S);
1346 HReg srcL = iselWordExpr_R(env, e->Iex.Binop.arg1);
1347 PPCRH* srcR = iselWordExpr_RH(env, syned, e->Iex.Binop.arg2);
1356 if (e->Iex.Binop.op == Iop_CmpORD64S
1357 || e->Iex.Binop.op == Iop_CmpORD64U) {
1358 Bool syned = toBool(e->Iex.Binop.op == Iop_CmpORD64S);
1360 HReg srcL = iselWordExpr_R(env, e->Iex.Binop.arg1);
1361 PPCRH* srcR = iselWordExpr_RH(env, syned, e->Iex.Binop.arg2);
1371 if (e->Iex.Binop.op == Iop_Max32U) {
1372 HReg r1 = iselWordExpr_R(env, e->Iex.Binop.arg1);
1373 HReg r2 = iselWordExpr_R(env, e->Iex.Binop.arg2);
1383 if (e->Iex.Binop.op == Iop_32HLto64) {
1384 HReg r_Hi = iselWordExpr_R(env, e->Iex.Binop.arg1);
1385 HReg r_Lo = iselWordExpr_R(env, e->Iex.Binop.arg2);
1400 if (e->Iex.Binop.op == Iop_CmpF64) {
1401 HReg fr_srcL = iselDblExpr(env, e->Iex.Binop.arg1);
1402 HReg fr_srcR = iselDblExpr(env, e->Iex.Binop.arg2);
1459 if (e->Iex.Binop.op == Iop_F64toI32S) {
1463 HReg fsrc = iselDblExpr(env, e->Iex.Binop.arg2);
1468 set_FPU_rounding_mode( env, e->Iex.Binop.arg1 );
1487 if (e->Iex.Binop.op == Iop_F64toI64S) {
1491 HReg fsrc = iselDblExpr(env, e->Iex.Binop.arg2);
1496 set_FPU_rounding_mode( env, e->Iex.Binop.arg1 );
2050 && e->Iex.Binop.op == Iop_Add64
2051 && e->Iex.Binop.arg2->tag == Iex_Const
2052 && e->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U64
2053 && (aligned4imm ? uLong_is_4_aligned(e->Iex.Binop.arg2
2056 && uLong_fits_in_16_bits(e->Iex.Binop.arg2
2058 return PPCAMode_IR( (Int)e->Iex.Binop.arg2->Iex.Const.con->Ico.U64,
2059 iselWordExpr_R(env, e->Iex.Binop.arg1) );
2064 && e->Iex.Binop.op == Iop_Add64) {
2065 HReg r_base = iselWordExpr_R(env, e->Iex.Binop.arg1);
2066 HReg r_idx = iselWordExpr_R(env, e->Iex.Binop.arg2);
2076 && e->Iex.Binop.op == Iop_Add32
2077 && e->Iex.Binop.arg2->tag == Iex_Const
2078 && e->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U32
2079 && uInt_fits_in_16_bits(e->Iex.Binop.arg2
2081 return PPCAMode_IR( (Int)e->Iex.Binop.arg2->Iex.Const.con->Ico.U32,
2082 iselWordExpr_R(env, e->Iex.Binop.arg1) );
2087 && e->Iex.Binop.op == Iop_Add32) {
2088 HReg r_base = iselWordExpr_R(env, e->Iex.Binop.arg1);
2089 HReg r_idx = iselWordExpr_R(env, e->Iex.Binop.arg2);
2387 && (e->Iex.Binop.op == Iop_CmpEQ32
2388 || e->Iex.Binop.op == Iop_CmpNE32
2389 || e->Iex.Binop.op == Iop_CmpLT32S
2390 || e->Iex.Binop.op == Iop_CmpLT32U
2391 || e->Iex.Binop.op == Iop_CmpLE32S
2392 || e->Iex.Binop.op == Iop_CmpLE32U)) {
2393 Bool syned = (e->Iex.Binop.op == Iop_CmpLT32S ||
2394 e->Iex.Binop.op == Iop_CmpLE32S);
2395 HReg r1 = iselWordExpr_R(env, e->Iex.Binop.arg1);
2396 PPCRH* ri2 = iselWordExpr_RH(env, syned, e->Iex.Binop.arg2);
2400 switch (e->Iex.Binop.op) {
2423 HReg r_src = iselWordExpr_R(env, e->Iex.Binop.arg1);
2434 && (e->Iex.Binop.op == Iop_CmpEQ64
2435 || e->Iex.Binop.op == Iop_CmpNE64
2436 || e->Iex.Binop.op == Iop_CmpLT64S
2437 || e->Iex.Binop.op == Iop_CmpLT64U
2438 || e->Iex.Binop.op == Iop_CmpLE64S
2439 || e->Iex.Binop.op == Iop_CmpLE64U)) {
2440 Bool syned = (e->Iex.Binop.op == Iop_CmpLT64S ||
2441 e->Iex.Binop.op == Iop_CmpLE64S);
2442 HReg r1 = iselWordExpr_R(env, e->Iex.Binop.arg1);
2443 PPCRH* ri2 = iselWordExpr_RH(env, syned, e->Iex.Binop.arg2);
2448 switch (e->Iex.Binop.op) {
2515 switch (e->Iex.Binop.op) {
2521 Bool syned = toBool(e->Iex.Binop.op == Iop_MullS64);
2522 HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1);
2523 HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2);
2537 *rHi = iselWordExpr_R(env, e->Iex.Binop.arg1);
2538 *rLo = iselWordExpr_R(env, e->Iex.Binop.arg2);
2673 IROp op_binop = e->Iex.Binop.op;
2681 HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1);
2682 HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2);
2703 iselInt64Expr(&xHi, &xLo, env, e->Iex.Binop.arg1);
2704 iselInt64Expr(&yHi, &yLo, env, e->Iex.Binop.arg2);
2717 iselInt64Expr(&xHi, &xLo, env, e->Iex.Binop.arg1);
2718 Binop.arg2);
2730 *rHi = iselWordExpr_R(env, e->Iex.Binop.arg1);
2731 *rLo = iselWordExpr_R(env, e->Iex.Binop.arg2);
2741 HReg fsrc = iselDblExpr(env, e->Iex.Binop.arg2);
2746 set_FPU_rounding_mode( env, e->Iex.Binop.arg1 );
3164 switch (e->Iex.Binop.op) {
3170 HReg fr_src = iselDblExpr(env, e->Iex.Binop.arg2);
3171 set_FPU_rounding_mode( env, e->Iex.Binop.arg1 );
3179 if (e->Iex.Binop.op == Iop_RoundF64toF32) {
3181 HReg r_src = iselDblExpr(env, e->Iex.Binop.arg2);
3182 set_FPU_rounding_mode( env, e->Iex.Binop.arg1 );
3188 if (e->Iex.Binop.op == Iop_I64StoF64) {
3191 HReg isrc = iselWordExpr_R(env, e->Iex.Binop.arg2);
3196 set_FPU_rounding_mode( env, e->Iex.Binop.arg1 );
3218 iselInt64Expr(&isrcHi, &isrcLo, env, e->Iex.Binop.arg2);
3221 set_FPU_rounding_mode( env, e->Iex.Binop.arg1 );
3451 return mk_AvDuplicateRI(env, e->Iex.Binop.arg1);
3459 switch (e->Iex.Binop.op) {
3477 iselInt64Expr(&r1, &r0, env, e->Iex.Binop.arg2);
3481 iselInt64Expr(&r3, &r2, env, e->Iex.Binop.arg1);
3491 HReg rHi = iselWordExpr_R(env, e->Iex.Binop.arg1);
3492 HReg rLo = iselWordExpr_R(env, e->Iex.Binop.arg2);
3526 HReg argL = iselVecExpr(env, e->Iex.Binop.arg1);
3527 HReg argR = iselVecExpr(env, e->Iex.Binop.arg2);
3534 HReg argL = iselVecExpr(env, e->Iex.Binop.arg1);
3535 HReg argR = iselVecExpr(env, e->Iex.Binop.arg2);
3559 HReg arg1 = iselVecExpr(env, e->Iex.Binop.arg1);
3560 HReg arg2 = iselVecExpr(env, e->Iex.Binop.arg2);
3590 HReg arg1 = iselVecExpr(env, e->Iex.Binop
3591 HReg arg2 = iselVecExpr(env, e->Iex.Binop.arg2);
3624 HReg arg1 = iselVecExpr(env, e->Iex.Binop.arg1);
3625 HReg arg2 = iselVecExpr(env, e->Iex.Binop.arg2);
3656 HReg arg1 = iselVecExpr(env, e->Iex.Binop.arg1);
3657 HReg arg2 = iselVecExpr(env, e->Iex.Binop.arg2);
3666 HReg r_src = iselVecExpr(env, e->Iex.Binop.arg1);
3668 HReg v_shft = mk_AvDuplicateRI(env, e->Iex.Binop.arg2);
3677 HReg r_src = iselVecExpr(env, e->Iex.Binop.arg1);
3679 HReg v_shft = mk_AvDuplicateRI(env, e->Iex.Binop.arg2);
3688 HReg r_src = iselVecExpr(env, e->Iex.Binop.arg1);
3690 HReg v_shft = mk_AvDuplicateRI(env, e->Iex.Binop.arg2);
3699 HReg r_src = iselVecExpr(env, e->Iex.Binop.arg1);
3700 HReg v_shft = mk_AvDuplicateRI(env, e->Iex.Binop.arg2);
3708 HReg v_src = iselVecExpr(env, e->Iex.Binop.arg1);
3709 HReg v_ctl = iselVecExpr(env, e->Iex.Binop.arg2);
3716 } /* switch (e->Iex.Binop.op) */
