| /external/llvm/lib/Target/ARM/ |
| ARMHazardRecognizer.cpp | 19 static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI,
30 return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI);
48 MachineInstr *DefMI = LastMI;
58 DefMI = &*I;
62 if (TII.isFpMLxInstruction(DefMI->getOpcode()) &&
64 hasRAWHazard(DefMI, MI, TRI))) {
|
| NEONMoveFix.cpp | 70 RegMap::iterator DefMI = Defs.find(SrcReg);
71 if (DefMI != Defs.end()) {
72 Domain = DefMI->second->getDesc().TSFlags & ARMII::DomainMask;
|
| MLxExpansionPass.cpp | 92 MachineInstr *DefMI = MRI->getVRegDef(Reg);
94 if (DefMI->getParent() != MBB)
96 if (DefMI->isCopyLike()) {
97 Reg = DefMI->getOperand(1).getReg();
99 DefMI = MRI->getVRegDef(Reg);
102 } else if (DefMI->isInsertSubreg()) {
103 Reg = DefMI->getOperand(2).getReg();
105 DefMI = MRI->getVRegDef(Reg);
111 return DefMI;
160 MachineInstr *DefMI = getAccDefMI(MI)
[all...] |
| /external/llvm/lib/CodeGen/ |
| LiveRangeEdit.cpp | 45 const MachineInstr *DefMI,
48 assert(DefMI && "Missing instruction");
50 if (!tii.isTriviallyReMaterializable(DefMI, aa))
64 MachineInstr *DefMI = lis.getInstructionFromIndex(VNI->def);
65 if (!DefMI)
67 checkRematerializable(VNI, DefMI, tii, aa);
167 MachineInstr *DefMI = 0, *UseMI = 0;
175 if (DefMI && DefMI != MI)
179 DefMI = MI
[all...] |
| PHIElimination.cpp | 131 MachineInstr *DefMI = *I;
132 unsigned DefReg = DefMI->getOperand(0).getReg();
134 DefMI->eraseFromParent();
173 const MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
174 if (!DefMI || !DefMI->isImplicitDef())
294 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
295 if (DefMI->isImplicitDef()) {
296 ImpDefs.insert(DefMI);
|
| PeepholeOptimizer.cpp | 294 MachineInstr *DefMI = MRI->getVRegDef(Src);
295 if (!DefMI || !DefMI->getDesc().isBitcast())
300 NumDefs = DefMI->getDesc().getNumDefs();
301 NumSrcs = DefMI->getDesc().getNumOperands() - NumDefs;
305 const MachineOperand &MO = DefMI->getOperand(i);
|
| MachineCSE.cpp | 125 MachineInstr *DefMI = MRI->getVRegDef(Reg);
126 if (DefMI->getParent() != MBB)
128 if (!DefMI->isCopy())
130 unsigned SrcReg = DefMI->getOperand(1).getReg();
133 if (DefMI->getOperand(0).getSubReg() || DefMI->getOperand(1).getSubReg())
137 DEBUG(dbgs() << "Coalescing: " << *DefMI);
141 DefMI->eraseFromParent();
|
| ScheduleDAGInstrs.cpp | 598 MachineInstr *DefMI = Def->getInstr();
599 int DefIdx = DefMI->findRegisterDefOperandIdx(Reg);
601 const MachineOperand &MO = DefMI->getOperand(DefIdx);
603 DefIdx >= (int)DefMI->getDesc().getNumOperands()) {
610 DefIdx = DefMI->findRegisterDefOperandIdx(Reg, false, true, TRI);
624 int UseCycle = TII->getOperandLatency(InstrItins, DefMI, DefIdx,
632 unsigned DefClass = DefMI->getDesc().getSchedClass();
|
| InlineSpiller.cpp | 92 MachineInstr *DefMI;
95 : AllDefsAreReloads(false), SpillReg(Reg), SpillVNI(VNI), DefMI(0) {}
412 SVI.DefMI = MI;
415 if (SeenOrigPHI || SVI.DefMI)
426 return SVI.DefMI;
449 MachineInstr *DefMI = 0;
455 DefMI = traceSiblingValue(Reg, VNI, OrigVNI);
457 if (!DefMI && !VNI->isPHIDef())
458 DefMI = LIS.getInstructionFromIndex(VNI->def);
459 if (DefMI && Edit->checkRematerializable(VNI, DefMI, TII, AA))
[all...] |
| StrongPHIElimination.cpp | 253 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
254 if (DefMI)
255 PHISrcDefs[DefMI->getParent()].push_back(DefMI);
[all...] |
| TailDuplication.cpp | 225 MachineInstr *DefMI = MRI->getVRegDef(VReg);
227 if (DefMI) {
228 DefBB = DefMI->getParent();
[all...] |
| TwoAddressInstructionPass.cpp | 91 MachineInstr *MI, MachineInstr *DefMI,
300 MachineInstr *MI, MachineInstr *DefMI,
326 return MBB == DefMI->getParent();
421 MachineInstr *DefMI = &MI;
423 if (!DefMI->killsRegister(Reg))
432 DefMI = &*Begin;
437 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
[all...] |
| LiveIntervalAnalysis.cpp | 277 MachineInstr *DefMI = getInstructionFromIndex(OldLR->valno->def);
278 if (DefMI != 0) {
279 return DefMI->findRegisterDefOperandIdx(interval.reg) != -1;
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
