| /external/llvm/utils/TableGen/ |
| TableGenBackend.cpp | 18 void TableGenBackend::EmitSourceFileHeader(const std::string &Desc,
21 " C++ -*-===//\n//\n// " << Desc << "\n//\n// Automatically generate"
|
| SubtargetEmitter.cpp | 94 const std::string &Desc = Feature->getValueAsString("Desc");
101 << "\"" << Desc << "\", "
|
| /external/llvm/include/llvm/MC/ |
| MCInstrInfo.h | 27 const MCInstrDesc *Desc; // Raw array to allow static init'n
28 unsigned NumOpcodes; // Number of entries in the desc array
34 Desc = D;
45 return Desc[Opcode];
|
| SubtargetFeature.h | 36 const char *Desc; // Help descriptor
|
| MCRegisterInfo.h | 55 const MCRegisterDesc *Desc; // Pointer to the descriptor array
68 Desc = D;
111 return Desc[RegNo];
|
| /external/javassist/src/main/javassist/runtime/ |
| Desc.java | 24 public class Desc {
57 + "' (Desc.useContextClassLoader: "
66 public static Class[] getParams(String desc) {
67 if (desc.charAt(0) != '(')
70 return getType(desc, desc.length(), 1, 0);
77 public static Class getType(String desc) {
78 Class[] result = getType(desc, desc.length(), 0, 0);
85 private static Class[] getType(String desc, int descLen
[all...] |
| /external/llvm/include/llvm/ADT/ |
| Statistic.h | 37 const char *Desc;
43 const char *getDesc() const { return Desc; }
46 void construct(const char *name, const char *desc) {
47 Name = name; Desc = desc;
118 #define STATISTIC(VARNAME, DESC) \
119 static llvm::Statistic VARNAME = { DEBUG_TYPE, DESC, 0, 0 }
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeMCCodeEmitter.cpp | 181 const MCInstrDesc &Desc = MCII.get(Opcode);
182 uint64_t TSFlags = Desc.TSFlags;
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrInfo.cpp | 299 const MCInstrDesc &Desc = MI->getDesc();
301 switch (Desc.TSFlags & MSP430II::SizeMask) {
303 switch (Desc.getOpcode()) {
|
| /external/llvm/lib/Target/X86/ |
| X86CodeEmitter.cpp | 71 void emitInstruction(MachineInstr &MI, const MCInstrDesc *Desc);
133 const MCInstrDesc &Desc = I->getDesc();
134 emitInstruction(*I, &Desc);
136 if (Desc.getOpcode() == X86::MOVPC32r)
151 const MCInstrDesc &Desc = MI.getDesc();
154 if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
156 if (Desc.TSFlags & X86II::REX_W)
159 unsigned NumOps = Desc.getNumOperands();
162 Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1;
175 switch (Desc.TSFlags & X86II::FormMask)
[all...] |
| X86MCCodeEmitter.cpp | 120 const MCInst &MI, const MCInstrDesc &Desc,
128 const MCInst &MI, const MCInstrDesc &Desc,
382 const MCInstrDesc &Desc,
589 const MCInstrDesc &Desc) {
599 Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1;
716 const MCInstrDesc &Desc,
776 if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc))
806 const MCInstrDesc &Desc = MCII.get(Opcode);
807 uint64_t TSFlags = Desc.TSFlags;
815 unsigned NumOps = Desc.getNumOperands()
[all...] |
| /external/llvm/include/llvm/Support/ |
| Registry.h | 22 const char *Name, *Desc;
27 : Name(N), Desc(D), Ctor(C)
31 const char *getDesc() const { return Desc; }
198 Add(const char *Name, const char *Desc)
199 : Entry(Name, Desc, CtorFn), Node(Entry) {}
|
| CommandLine.h | 262 // desc - Modifier to set the description shown in the -help output...
263 struct desc { struct in namespace:llvm::cl
264 const char *Desc;
265 desc(const char *Str) : Desc(Str) {} function in struct:llvm::cl::desc
266 void apply(Option &O) const { O.setDescription(Desc); }
272 const char *Desc;
273 value_desc(const char *Str) : Desc(Str) {}
274 void apply(Option &O) const { O.setValueStr(Desc); }
430 #define clEnumVal(ENUMVAL, DESC) #ENUMVAL, int(ENUMVAL), DES
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.cpp | 49 cl::desc("Force use of virtual base registers for stack load/store"));
52 cl::desc("Enable pre-regalloc stack frame index allocation"));
55 cl::desc("Enable use of a base pointer for complex stack frames"));
947 const MCInstrDesc &Desc = MI->getDesc();
948 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
[all...] |
| ARMExpandPseudoInsts.cpp | 71 const MCInstrDesc &Desc = OldMI.getDesc();
72 for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands();
[all...] |
| ARMMCCodeEmitter.cpp | [all...] |
| ARMBaseInstrInfo.cpp | 46 cl::desc("Enable ARM 2-addr to 3-addr conv"));
[all...] |
| /external/clang/include/clang/StaticAnalyzer/Core/BugReporter/ |
| PathDiagnostic.h | 369 std::string Desc;
376 PathDiagnostic(llvm::StringRef bugtype, llvm::StringRef desc,
381 llvm::StringRef getDescription() const { return Desc; }
|
| /external/jhead/ |
| jhead.h | 155 char * Desc;
|
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| DwarfDebug.cpp | 49 cl::desc("Print DbgScope information for each machine instruction"));
53 cl::desc("Disable debug info printing"));
56 cl::desc("Make an absence of debug location information explicit."),
134 DIDescriptor Desc; // Debug info descriptor for scope.
150 : Parent(P), Desc(D), InlinedAtLocation(I), AbstractScope(false),
158 DIDescriptor getDesc() const { return Desc; }
160 const MDNode *getScopeNode() const { return Desc; }
233 const MDNode *N = Desc;
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGRRList.cpp | 71 cl::desc("Disable cycle-level precision during preRA scheduling"));
77 cl::desc("Disable regpressure priority in sched=list-ilp"));
80 cl::desc("Disable live use priority in sched=list-ilp"));
83 cl::desc("Disable virtual register cycle interference checks"));
86 cl::desc("Disable physreg def-use affinity"));
89 cl::desc("Disable no-stall priority in sched=list-ilp"));
92 cl::desc("Disable critical path priority in sched=list-ilp"));
95 cl::desc("Disable scheduled-height priority in sched=list-ilp"));
99 cl::desc("Number of instructions to allow ahead of the critical path "
104 cl::desc("Average inst/cycle whan no target itinerary exists."))
[all...] |
