| /external/llvm/utils/TableGen/ |
| PseudoLoweringEmitter.h | 23 enum MapKind { Operand, Imm, Reg };
27 uint64_t Imm; // Integer immedate value.
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| CodeGenInstruction.h | 285 int64_t Imm;
294 ResultOperand(int64_t I) : Imm(I), Kind(K_Imm) {}
303 int64_t getImm() const { assert(isImm()); return Imm; }
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| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelDAGToDAG.cpp | 89 inline SDValue getI32Imm(unsigned Imm) {
90 return CurDAG->getTargetConstant(Imm, MVT::i32);
100 static bool isIntS32Immediate(SDNode *N, int32_t &Imm) {
105 Imm = (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
107 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
109 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
112 static bool isIntS32Immediate(SDValue Op, int32_t &Imm) {
113 return isIntS32Immediate(Op.getNode(), Imm);
119 /// can be more efficiently represented with [r+imm].
127 int32_t imm = 0
154 int32_t imm = 0; local
209 SDValue imm = CurDAG->getTargetConstant(0, MVT::i32); local
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMAddressingModes.h | 70 //case ISD::ROTL: // Only if imm -> turn into ROTR.
117 // reg [asr|lsl|lsr|ror|rrx] imm
120 // reg, the second is the shift amount (or reg0 if not present or imm). The
121 // third operand encodes the shift opcode and the imm if a reg isn't present.
123 static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) {
124 return ShOp | (Imm << 3);
133 /// getSOImmValImm - Given an encoded imm field for the reg/imm form, return
134 /// the 8-bit imm value.
135 static inline unsigned getSOImmValImm(unsigned Imm) {
[all...] |
| ARMExpandPseudoInsts.cpp | [all...] |
| Thumb2SizeReduction.cpp | 490 unsigned Imm = MI->getOperand(2).getImm();
494 if (Imm & 3 || Imm > 1020)
509 .addImm(Imm / 4); // The tADDrSPi has an implied scale by four.
597 unsigned Imm = MI->getOperand(2).getImm();
599 if (Imm > Limit)
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| ARMAsmPrinter.cpp | 270 int64_t Imm = MO.getImm();
278 O << Imm;
[all...] |
| ARMMCCodeEmitter.cpp | 81 unsigned &Reg, unsigned &Imm,
146 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
429 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
432 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const {
451 Imm = SImm;
710 // {20-16} = imm{15-12}
711 // {11-0} = imm{11-0}
774 // {11-7} = imm
806 unsigned Imm = MO1.getImm();
807 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add
[all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/MBlaze/AsmParser/ |
| MBlazeAsmParser.cpp | 100 } Imm;
124 Imm = o.Imm;
151 return Imm.Val;
243 Op->Imm.Val = Val;
251 Op->Imm.Val = Val;
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| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelDAGToDAG.cpp | 103 inline SDValue getI8Imm(uint64_t Imm) {
104 return CurDAG->getTargetConstant(Imm, MVT::i8);
109 inline SDValue getI16Imm(uint64_t Imm) {
110 return CurDAG->getTargetConstant(Imm, MVT::i16);
115 inline SDValue getI32Imm(uint64_t Imm) {
116 return CurDAG->getTargetConstant(Imm, MVT::i32);
159 static bool isImmSExt20(int64_t Val, int64_t &Imm) {
161 Imm = Val;
171 static bool isImmZExt12(int64_t Val, int64_t &Imm) {
173 Imm = Val
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86RegisterInfo.cpp | 468 static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) {
470 if (isInt<8>(Imm))
474 if (isInt<8>(Imm))
480 static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) {
482 if (isInt<8>(Imm))
486 if (isInt<8>(Imm))
611 int Imm = (int)(MI.getOperand(i + 3).getImm());
612 int Offset = FIOffset + Imm;
613 assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
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| X86ISelDAGToDAG.cpp | 265 inline SDValue getI8Imm(unsigned Imm) {
266 return CurDAG->getTargetConstant(Imm, MVT::i8);
271 inline SDValue getI32Imm(unsigned Imm) {
272 return CurDAG->getTargetConstant(Imm, MVT::i32);
333 if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(Op1))
334 if (Imm->getAPIntValue().isSignedIntN(8))
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | 365 uint64_t Imm = CI->getZExtValue();
370 isPowerOf2_64(Imm)) {
371 Imm = Log2_64(Imm);
376 Op0IsKill, Imm, VT.getSimpleVT());
[all...] |
| TargetLowering.cpp | [all...] |
| SelectionDAG.cpp | 897 APInt Imm = APInt::getLowBitsSet(BitWidth,
900 getConstant(Imm, Op.getValueType()));
[all...] |
| DAGCombiner.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 63 inline SDValue getI32Imm(unsigned Imm) {
64 return CurDAG->getTargetConstant(Imm, MVT::i32);
69 inline SDValue getI64Imm(uint64_t Imm) {
70 return CurDAG->getTargetConstant(Imm, MVT::i64);
74 inline SDValue getSmallIPtrImm(unsigned Imm) {
75 return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy());
105 /// a base register plus a signed 16-bit displacement [r+imm].
121 /// be represented by [r+imm], which are preferred.
133 /// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable
259 static bool isIntS16Immediate(SDNode *N, short &Imm) {
[all...] |
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | 126 } Imm;
164 return Imm.Val;
315 Res->Imm.Val = Val;
[all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassemblerCore.cpp | 850 // SOImm is 4-bit rotate amount in bits 11-8 with 8-bit imm in bits 7-0.
854 unsigned Imm = insn & 0xFF;
855 MI.addOperand(MCOperand::CreateImm(ARM_AM::rotr32(Imm, 2*Rot)));
877 assert(NumOps >= 1 && OpInfo[0].RegClass < 0 && "Imm operand expected");
930 assert(NumOps >= 1 && OpInfo[0].RegClass < 0 && "Imm operand expected");
2177 double imm = Opcode == ARM::FCONSTD ? immFP.convertToDouble() : local
[all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 206 } Imm;
228 unsigned Imm;
265 Imm = o.Imm;
321 return Imm.Val;
881 Op->Imm.Val = Val;
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| LoopStrengthReduce.cpp | 389 OS << "imm(" << UnfoldedOffset << ')';
837 OS << ", plus " << ImmCost << " imm cost";
[all...] |
| /external/valgrind/main/VEX/priv/ |
| host_amd64_defs.h | 139 UInt imm; member in struct:__anon11667::__anon11668::__anon11669
143 UInt imm; member in struct:__anon11667::__anon11668::__anon11670
176 } Imm;
210 } Imm;
|
| host_ppc_defs.h | 244 } Imm;
272 ULong Imm;
484 Pin_AvShlDbl, /* AV shift-left double by imm */
|
| host_x86_defs.h | 123 UInt imm; member in struct:__anon11908::__anon11909::__anon11910
127 UInt imm; member in struct:__anon11908::__anon11909::__anon11911
160 } Imm;
194 } Imm;
|
