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    Searched defs:RegClass (Results 1 - 6 of 6) sorted by null

  /external/llvm/lib/Target/
TargetInstrInfo.cpp 36 short RegClass = MCID.OpInfo[OpNum].RegClass;
38 return TRI->getPointerRegClass(RegClass);
41 if (RegClass < 0)
45 return TRI->getRegClass(RegClass);
  /external/llvm/lib/CodeGen/
RegisterClassInfo.h 40 OwningArrayPtr<RCInfo> RegClass;
64 const RCInfo &RCI = RegClass[RC->getID()];
  /external/llvm/include/llvm/MC/
MCInstrDesc.h 57 /// RegClass - This specifies the register class enumeration of the operand
61 short RegClass;
  /external/llvm/lib/Target/ARM/
ARMISelDAGToDAG.cpp     [all...]
  /external/llvm/lib/Target/ARM/Disassembler/
ARMDisassemblerCore.cpp 84 // Return the register enum Based on RegClass and the raw register number.
602 && OpInfo[0].RegClass == ARM::GPRRegClassID
603 && OpInfo[1].RegClass == ARM::GPRRegClassID
604 && OpInfo[2].RegClass == ARM::GPRRegClassID
613 assert(NumOps >= 4 && OpInfo[3].RegClass == ARM::GPRRegClassID &&
633 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) {
812 assert(NumOps >= 1 && OpInfo[0].RegClass == ARM::GPRRegClassID &&
821 assert(NumOps >= 1 && OpInfo[0].RegClass == ARM::GPRRegClassID &&
831 assert(NumOps >= 1 && OpInfo[1].RegClass == ARM::GPRRegClassID &&
877 assert(NumOps >= 1 && OpInfo[0].RegClass < 0 && "Imm operand expected")
    [all...]
  /external/llvm/utils/TableGen/
CodeGenDAGPatterns.cpp     [all...]

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