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    Searched defs:Registers (Results 1 - 8 of 8) sorted by null

  /external/llvm/utils/TableGen/
CodeGenRegisters.h 46 // Get a map of sub-registers computed lazily.
47 // This includes unique entries for all sub-sub-registers.
51 assert(SubRegsComplete && "Must precompute sub-registers");
55 // Add sub-registers to OSet following a pre-order defined by the .td file.
58 // List of super-registers in topological order, small to large.
61 // Get the list of super-registers.
62 // This is only valid after computeDerivedInfo has visited all registers.
64 assert(SubRegsComplete && "Must precompute sub-registers");
121 // 1. All RC registers are also in this.
128 // The order of registers is the same as in the .td file
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RegisterInfoEmitter.cpp 27 // runEnums - Print out enum values for all of the registers.
31 const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters();
33 std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace");
46 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
47 OS << " " << Registers[i]->getName() << " = " <<
48 Registers[i]->EnumValue << ",\n";
49 assert(Registers.size() == Registers[Registers.size()-1]->EnumValue &&
51 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n"
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AsmWriterEmitter.cpp 464 const std::vector<CodeGenRegister*> &Registers) {
467 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
468 const CodeGenRegister &Reg = *Registers[i];
519 const std::vector<CodeGenRegister*> &Registers =
533 O << " assert(RegNo && RegNo < " << (Registers.size()+1)
539 emitRegisterNameString(O, AltNameIndices[i]->getName(), Registers);
541 emitRegisterNameString(O, "", Registers);
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AsmMatcherEmitter.cpp 175 /// For register classes, the records for all the registers in this class.
176 std::set<Record*> Registers;
196 // Registers classes are only related to registers classes, and only if
204 std::set_intersection(Registers.begin(), Registers.end(),
205 RHS.Registers.begin(), RHS.Registers.end(),
661 // Collect singleton registers, if used.
915 const std::vector<CodeGenRegister*> &Registers
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  /external/grub/netboot/
3c90x.c 54 enum Registers
83 /** following are windowed registers **/
771 /** Program the MAC address into the station address registers **/
  /external/llvm/lib/Target/ARM/AsmParser/
ARMAsmParser.cpp 172 SmallVector<unsigned, 8> Registers;
258 Registers = o.Registers;
316 return Registers;
872 Op->Registers.push_back(I->first);
873 array_pod_sort(Op->Registers.begin(), Op->Registers.end());
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  /external/v8/src/arm/
constants-arm.h 94 // Number of registers in normal ARM mode.
442 // These constants are declared in assembler-arm.cc, as they use named registers
739 class Registers {
  /external/v8/src/mips/
constants-mips.h 61 // Registers and FPURegister.
63 // Number of general purpose registers.
67 // Number of registers with HI, LO, and pc.
73 // Number coprocessor registers.
77 // FPU (coprocessor 1) control registers. Currently only FCSR is implemented.
87 class Registers {
488 // registers and other constants.

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