| /external/clang/test/Parser/ |
| cxx-using-declaration.cpp | 4 int VA;
9 using A::VA;
15 VA = 1;
|
| /external/clang/test/Preprocessor/ |
| macro_paste_bad.c | 32 #define VA __VA_ ## ARGS__
33 int VA; // expected-warning {{__VA_ARGS__ can only appear in the expansion of a C99 variadic macro}}
|
| /external/llvm/lib/Target/PTX/ |
| PTXISelLowering.cpp | 245 CCValAssign& VA = ArgLocs[i];
246 EVT RegVT = VA.getLocVT();
249 assert(VA.isRegLoc() && "CCValAssign must be RegLoc");
275 MF.getRegInfo().addLiveIn(VA.getLocReg(), Reg);
280 MFI->addArgReg(VA.getLocReg());
324 CCValAssign& VA = RVLocs[i];
326 assert(VA.isRegLoc() && "CCValAssign must be RegLoc");
328 unsigned Reg = VA.getLocReg();
|
| /external/clang/test/CXX/special/class.dtor/ |
| p3-0x.cpp | 140 struct VA {
142 virtual ~VA() {}
145 struct VB : VA
149 struct TVB : VA
|
| /external/llvm/lib/Target/Blackfin/ |
| BlackfinISelLowering.cpp | 180 CCValAssign &VA = ArgLocs[i];
182 if (VA.isRegLoc()) {
183 EVT RegVT = VA.getLocVT();
184 TargetRegisterClass *RC = VA.getLocReg() == BF::P0 ?
186 assert(RC->contains(VA.getLocReg()) && "Unexpected regclass in CCState");
190 MF.getRegInfo().addLiveIn(VA.getLocReg(), Reg);
196 if (VA.getLocInfo() == CCValAssign::SExt)
198 DAG.getValueType(VA.getValVT()));
199 else if (VA.getLocInfo() == CCValAssign::ZExt)
201 DAG.getValueType(VA.getValVT()))
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 305 CCValAssign &VA = ArgLocs[i];
306 EVT LocVT = VA.getLocVT();
307 if (VA.isRegLoc()) {
330 RegInfo.addLiveIn(VA.getLocReg(), VReg);
334 assert(VA.isMemLoc());
339 VA.getLocMemOffset(), true);
352 if (VA.getLocInfo() == CCValAssign::SExt)
354 DAG.getValueType(VA.getValVT()));
355 else if (VA.getLocInfo() == CCValAssign::ZExt)
357 DAG.getValueType(VA.getValVT()))
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 719 CCValAssign &VA = ArgLocs[i];
720 MVT RegVT = VA.getLocVT();
724 switch (VA.getLocInfo()) {
740 if (VA.isRegLoc()) {
741 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
744 assert(VA.isMemLoc());
752 unsigned ArgSize = VA.getValVT().getSizeInBits()/8;
753 unsigned StackLoc = VA.getLocMemOffset() + 4;
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 322 CCValAssign &VA = ArgLocs[i];
323 if (VA.isRegLoc()) {
325 EVT RegVT = VA.getLocVT();
338 RegInfo.addLiveIn(VA.getLocReg(), VReg);
344 if (VA.getLocInfo() == CCValAssign::SExt)
346 DAG.getValueType(VA.getValVT()));
347 else if (VA.getLocInfo() == CCValAssign::ZExt)
349 DAG.getValueType(VA.getValVT()));
351 if (VA.getLocInfo() != CCValAssign::Full)
352 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue)
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombinePHI.cpp | [all...] |
| /external/llvm/lib/Target/Alpha/ |
| AlphaISelLowering.cpp | 253 CCValAssign &VA = ArgLocs[i];
258 switch (VA.getLocInfo()) {
262 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
265 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
268 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
274 if (VA.isRegLoc()) {
275 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
277 assert(VA.isMemLoc());
284 DAG.getIntPtrConstant(VA.getLocMemOffset()));
357 CCValAssign &VA = RVLocs[i]
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 111 CCValAssign &VA = RVLocs[i];
112 assert(VA.isRegLoc() && "Can only return in registers!");
114 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
170 CCValAssign &VA = ArgLocs[i];
183 if (VA.isRegLoc()) {
184 if (VA.needsCustom()) {
185 assert(VA.getLocVT() == MVT::f64);
187 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi);
213 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg);
215 if (VA.getLocVT() == MVT::f32
[all...] |
| /external/llvm/lib/VMCore/ |
| Verifier.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | [all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | 723 CCValAssign &VA = ValLocs[0];
726 if (VA.getLocInfo() != CCValAssign::Full)
729 if (!VA.isRegLoc())
734 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
737 unsigned SrcReg = Reg + VA.getValNo();
739 EVT DstVT = VA.getValVT();
763 unsigned DstReg = VA.getLocReg();
772 MRI.addLiveOut(VA.getLocReg());
[all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
| /external/qemu/ |
| ppc-dis.c | 820 /* The VA field in a VA, VX or VXR form instruction. */
821 #define VA UI + 1
824 /* The VB field in a VA, VX or VXR form instruction. */
825 #define VB VA + 1
828 /* The VC field in a VA form instruction. */
832 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
846 /* The SHB field in a VA form instruction. */
[all...] |
