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    Searched defs:baseReg (Results 1 - 5 of 5) sorted by null

  /external/llvm/lib/MC/MCDisassembler/
EDOperand.cpp 162 unsigned baseReg = Inst.Inst->getOperand(MCOpIndex).getReg();
183 if (baseReg) {
185 if (callback(&baseVal, baseReg, arg))
  /external/llvm/lib/Target/X86/Disassembler/
X86Disassembler.cpp 258 // 1. basereg (register) The R/M base, or (if there is a SIB) the
269 MCOperand baseReg;
283 baseReg = MCOperand::CreateReg(X86::x); break;
288 baseReg = MCOperand::CreateReg(0);
316 baseReg = MCOperand::CreateReg(X86::RIP); // Section 2.2.1.6
318 baseReg = MCOperand::CreateReg(0);
323 baseReg = MCOperand::CreateReg(X86::BX);
327 baseReg = MCOperand::CreateReg(X86::BX);
331 baseReg = MCOperand::CreateReg(X86::BP);
335 baseReg = MCOperand::CreateReg(X86::BP)
    [all...]
  /external/webkit/Source/JavaScriptCore/dfg/
DFGSpeculativeJIT.cpp 558 MacroAssembler::RegisterID baseReg = base.registerID();
564 m_jit.loadPtr(MacroAssembler::Address(baseReg, JSArray::storageOffset()), storageReg);
567 speculationCheck(m_jit.branchPtr(MacroAssembler::NotEqual, MacroAssembler::Address(baseReg), MacroAssembler::TrustedImmPtr(m_jit.globalData()->jsArrayVPtr)));
568 speculationCheck(m_jit.branch32(MacroAssembler::AboveOrEqual, propertyReg, MacroAssembler::Address(baseReg, JSArray::vectorLengthOffset())));
588 MacroAssembler::RegisterID baseReg = base.registerID();
594 speculationCheck(m_jit.branchPtr(MacroAssembler::NotEqual, MacroAssembler::Address(baseReg), MacroAssembler::TrustedImmPtr(m_jit.globalData()->jsArrayVPtr)));
595 speculationCheck(m_jit.branch32(MacroAssembler::AboveOrEqual, propertyReg, MacroAssembler::Address(baseReg, JSArray::vectorLengthOffset())));
598 m_jit.loadPtr(MacroAssembler::Address(baseReg, JSArray::storageOffset()), storageReg);
  /external/clang/lib/StaticAnalyzer/Core/
RegionStore.cpp 833 const MemRegion *baseReg =
836 return loc::MemRegionVal(baseReg);
    [all...]
ExprEngine.cpp 362 const MemRegion *baseReg = baseVal.getAsRegion();
363 assert(baseReg);
366 VisitCXXConstructExpr(ctorExpr, baseReg, pred, dst);
    [all...]

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