1 //==-- PPCFrameLowering.h - Define frame lowering for PowerPC ----*- C++ -*-==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef POWERPC_FRAMEINFO_H 14 #define POWERPC_FRAMEINFO_H 15 16 #include "PPC.h" 17 #include "PPCSubtarget.h" 18 #include "llvm/Target/TargetFrameLowering.h" 19 #include "llvm/Target/TargetMachine.h" 20 #include "llvm/ADT/STLExtras.h" 21 22 namespace llvm { 23 class PPCSubtarget; 24 25 class PPCFrameLowering: public TargetFrameLowering { 26 const PPCSubtarget &Subtarget; 27 28 public: 29 PPCFrameLowering(const PPCSubtarget &sti) 30 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 16, 0), 31 Subtarget(sti) { 32 } 33 34 void determineFrameLayout(MachineFunction &MF) const; 35 36 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into 37 /// the function. 38 void emitPrologue(MachineFunction &MF) const; 39 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; 40 41 bool hasFP(const MachineFunction &MF) const; 42 bool needsFP(const MachineFunction &MF) const; 43 44 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 45 RegScavenger *RS = NULL) const; 46 void processFunctionBeforeFrameFinalized(MachineFunction &MF) const; 47 48 /// targetHandlesStackFrameRounding - Returns true if the target is 49 /// responsible for rounding up the stack frame (probably at emitPrologue 50 /// time). 51 bool targetHandlesStackFrameRounding() const { return true; } 52 53 /// getReturnSaveOffset - Return the previous frame offset to save the 54 /// return address. 55 static unsigned getReturnSaveOffset(bool isPPC64, bool isDarwinABI) { 56 if (isDarwinABI) 57 return isPPC64 ? 16 : 8; 58 // SVR4 ABI: 59 return isPPC64 ? 16 : 4; 60 } 61 62 /// getFramePointerSaveOffset - Return the previous frame offset to save the 63 /// frame pointer. 64 static unsigned getFramePointerSaveOffset(bool isPPC64, bool isDarwinABI) { 65 // For the Darwin ABI: 66 // We cannot use the TOC save slot (offset +20) in the PowerPC linkage area 67 // for saving the frame pointer (if needed.) While the published ABI has 68 // not used this slot since at least MacOSX 10.2, there is older code 69 // around that does use it, and that needs to continue to work. 70 if (isDarwinABI) 71 return isPPC64 ? -8U : -4U; 72 73 // SVR4 ABI: First slot in the general register save area. 74 return isPPC64 ? -8U : -4U; 75 } 76 77 /// getLinkageSize - Return the size of the PowerPC ABI linkage area. 78 /// 79 static unsigned getLinkageSize(bool isPPC64, bool isDarwinABI) { 80 if (isDarwinABI || isPPC64) 81 return 6 * (isPPC64 ? 8 : 4); 82 83 // SVR4 ABI: 84 return 8; 85 } 86 87 /// getMinCallArgumentsSize - Return the size of the minium PowerPC ABI 88 /// argument area. 89 static unsigned getMinCallArgumentsSize(bool isPPC64, bool isDarwinABI) { 90 // For the Darwin ABI / 64-bit SVR4 ABI: 91 // The prolog code of the callee may store up to 8 GPR argument registers to 92 // the stack, allowing va_start to index over them in memory if its varargs. 93 // Because we cannot tell if this is needed on the caller side, we have to 94 // conservatively assume that it is needed. As such, make sure we have at 95 // least enough stack space for the caller to store the 8 GPRs. 96 if (isDarwinABI || isPPC64) 97 return 8 * (isPPC64 ? 8 : 4); 98 99 // 32-bit SVR4 ABI: 100 // There is no default stack allocated for the 8 first GPR arguments. 101 return 0; 102 } 103 104 /// getMinCallFrameSize - Return the minimum size a call frame can be using 105 /// the PowerPC ABI. 106 static unsigned getMinCallFrameSize(bool isPPC64, bool isDarwinABI) { 107 // The call frame needs to be at least big enough for linkage and 8 args. 108 return getLinkageSize(isPPC64, isDarwinABI) + 109 getMinCallArgumentsSize(isPPC64, isDarwinABI); 110 } 111 112 // With the SVR4 ABI, callee-saved registers have fixed offsets on the stack. 113 const SpillSlot * 114 getCalleeSavedSpillSlots(unsigned &NumEntries) const { 115 if (Subtarget.isDarwinABI()) { 116 NumEntries = 1; 117 if (Subtarget.isPPC64()) { 118 static const SpillSlot darwin64Offsets = {PPC::X31, -8}; 119 return &darwin64Offsets; 120 } else { 121 static const SpillSlot darwinOffsets = {PPC::R31, -4}; 122 return &darwinOffsets; 123 } 124 } 125 126 // Early exit if not using the SVR4 ABI. 127 if (!Subtarget.isSVR4ABI()) { 128 NumEntries = 0; 129 return 0; 130 } 131 132 static const SpillSlot Offsets[] = { 133 // Floating-point register save area offsets. 134 {PPC::F31, -8}, 135 {PPC::F30, -16}, 136 {PPC::F29, -24}, 137 {PPC::F28, -32}, 138 {PPC::F27, -40}, 139 {PPC::F26, -48}, 140 {PPC::F25, -56}, 141 {PPC::F24, -64}, 142 {PPC::F23, -72}, 143 {PPC::F22, -80}, 144 {PPC::F21, -88}, 145 {PPC::F20, -96}, 146 {PPC::F19, -104}, 147 {PPC::F18, -112}, 148 {PPC::F17, -120}, 149 {PPC::F16, -128}, 150 {PPC::F15, -136}, 151 {PPC::F14, -144}, 152 153 // General register save area offsets. 154 {PPC::R31, -4}, 155 {PPC::R30, -8}, 156 {PPC::R29, -12}, 157 {PPC::R28, -16}, 158 {PPC::R27, -20}, 159 {PPC::R26, -24}, 160 {PPC::R25, -28}, 161 {PPC::R24, -32}, 162 {PPC::R23, -36}, 163 {PPC::R22, -40}, 164 {PPC::R21, -44}, 165 {PPC::R20, -48}, 166 {PPC::R19, -52}, 167 {PPC::R18, -56}, 168 {PPC::R17, -60}, 169 {PPC::R16, -64}, 170 {PPC::R15, -68}, 171 {PPC::R14, -72}, 172 173 // CR save area offset. 174 // FIXME SVR4: Disable CR save area for now. 175 // {PPC::CR2, -4}, 176 // {PPC::CR3, -4}, 177 // {PPC::CR4, -4}, 178 // {PPC::CR2LT, -4}, 179 // {PPC::CR2GT, -4}, 180 // {PPC::CR2EQ, -4}, 181 // {PPC::CR2UN, -4}, 182 // {PPC::CR3LT, -4}, 183 // {PPC::CR3GT, -4}, 184 // {PPC::CR3EQ, -4}, 185 // {PPC::CR3UN, -4}, 186 // {PPC::CR4LT, -4}, 187 // {PPC::CR4GT, -4}, 188 // {PPC::CR4EQ, -4}, 189 // {PPC::CR4UN, -4}, 190 191 // VRSAVE save area offset. 192 {PPC::VRSAVE, -4}, 193 194 // Vector register save area 195 {PPC::V31, -16}, 196 {PPC::V30, -32}, 197 {PPC::V29, -48}, 198 {PPC::V28, -64}, 199 {PPC::V27, -80}, 200 {PPC::V26, -96}, 201 {PPC::V25, -112}, 202 {PPC::V24, -128}, 203 {PPC::V23, -144}, 204 {PPC::V22, -160}, 205 {PPC::V21, -176}, 206 {PPC::V20, -192} 207 }; 208 209 static const SpillSlot Offsets64[] = { 210 // Floating-point register save area offsets. 211 {PPC::F31, -8}, 212 {PPC::F30, -16}, 213 {PPC::F29, -24}, 214 {PPC::F28, -32}, 215 {PPC::F27, -40}, 216 {PPC::F26, -48}, 217 {PPC::F25, -56}, 218 {PPC::F24, -64}, 219 {PPC::F23, -72}, 220 {PPC::F22, -80}, 221 {PPC::F21, -88}, 222 {PPC::F20, -96}, 223 {PPC::F19, -104}, 224 {PPC::F18, -112}, 225 {PPC::F17, -120}, 226 {PPC::F16, -128}, 227 {PPC::F15, -136}, 228 {PPC::F14, -144}, 229 230 // General register save area offsets. 231 // FIXME 64-bit SVR4: Are 32-bit registers actually allocated in 64-bit 232 // mode? 233 {PPC::R31, -4}, 234 {PPC::R30, -12}, 235 {PPC::R29, -20}, 236 {PPC::R28, -28}, 237 {PPC::R27, -36}, 238 {PPC::R26, -44}, 239 {PPC::R25, -52}, 240 {PPC::R24, -60}, 241 {PPC::R23, -68}, 242 {PPC::R22, -76}, 243 {PPC::R21, -84}, 244 {PPC::R20, -92}, 245 {PPC::R19, -100}, 246 {PPC::R18, -108}, 247 {PPC::R17, -116}, 248 {PPC::R16, -124}, 249 {PPC::R15, -132}, 250 {PPC::R14, -140}, 251 252 {PPC::X31, -8}, 253 {PPC::X30, -16}, 254 {PPC::X29, -24}, 255 {PPC::X28, -32}, 256 {PPC::X27, -40}, 257 {PPC::X26, -48}, 258 {PPC::X25, -56}, 259 {PPC::X24, -64}, 260 {PPC::X23, -72}, 261 {PPC::X22, -80}, 262 {PPC::X21, -88}, 263 {PPC::X20, -96}, 264 {PPC::X19, -104}, 265 {PPC::X18, -112}, 266 {PPC::X17, -120}, 267 {PPC::X16, -128}, 268 {PPC::X15, -136}, 269 {PPC::X14, -144}, 270 271 // CR save area offset. 272 // FIXME SVR4: Disable CR save area for now. 273 // {PPC::CR2, -4}, 274 // {PPC::CR3, -4}, 275 // {PPC::CR4, -4}, 276 // {PPC::CR2LT, -4}, 277 // {PPC::CR2GT, -4}, 278 // {PPC::CR2EQ, -4}, 279 // {PPC::CR2UN, -4}, 280 // {PPC::CR3LT, -4}, 281 // {PPC::CR3GT, -4}, 282 // {PPC::CR3EQ, -4}, 283 // {PPC::CR3UN, -4}, 284 // {PPC::CR4LT, -4}, 285 // {PPC::CR4GT, -4}, 286 // {PPC::CR4EQ, -4}, 287 // {PPC::CR4UN, -4}, 288 289 // VRSAVE save area offset. 290 {PPC::VRSAVE, -4}, 291 292 // Vector register save area 293 {PPC::V31, -16}, 294 {PPC::V30, -32}, 295 {PPC::V29, -48}, 296 {PPC::V28, -64}, 297 {PPC::V27, -80}, 298 {PPC::V26, -96}, 299 {PPC::V25, -112}, 300 {PPC::V24, -128}, 301 {PPC::V23, -144}, 302 {PPC::V22, -160}, 303 {PPC::V21, -176}, 304 {PPC::V20, -192} 305 }; 306 307 if (Subtarget.isPPC64()) { 308 NumEntries = array_lengthof(Offsets64); 309 310 return Offsets64; 311 } else { 312 NumEntries = array_lengthof(Offsets); 313 314 return Offsets; 315 } 316 } 317 }; 318 319 } // End llvm namespace 320 321 #endif 322
