| /frameworks/base/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/vc/m4p10/src/ |
| armVCM4P10_InterpolateLuma_Copy_unsafe_s.s | 34 srcStep RN 1
62 M_LDR x0, [pSrc], srcStep
63 M_LDR x1, [pSrc], srcStep
65 M_LDR x2, [pSrc], srcStep
67 M_LDR x3, [pSrc], srcStep
74 M_LDR x0, [pSrc], srcStep
76 M_LDR x2, [pSrc], srcStep
83 M_LDR x0, [pSrc], srcStep
86 M_LDR x2, [pSrc], srcStep
97 M_LDR x0, [pSrc], srcStep
[all...] |
| armVCM4P10_InterpolateLuma_Align_unsafe_s.s | 27 srcStep RN 1
78 ADD pSrc, pSrc, srcStep
89 ADD pSrc, pSrc, srcStep
105 ADD pSrc, pSrc, srcStep
121 ADD pSrc, pSrc, srcStep
136 MOV srcStep, #12
178 M_LDR x0, [pSrc], srcStep
189 M_LDR x0, [pSrc], srcStep
202 M_LDR x0, [pSrc], srcStep
215 M_LDR x0, [pSrc], srcStep
[all...] |
| armVCM4P10_InterpolateLuma_HalfHor4x4_unsafe_s.s | 46 srcStep RN 1
85 M_STR srcStep, pSrcStep
89 LDR ValD, [pSrc, srcStep] ;// Load row 1 [d1 c1 b1 a1]
91 LDR ValH, [pSrc, srcStep] ;// Load [h1 g1 f1 e1]
93 LDRB Temp2, [pSrc, srcStep] ;// Load row 1 [l1 k1 j1 i1]
164 M_LDR srcStep, pSrcStep
169 ADD pSrc, pSrc, srcStep, LSL #1
174 SUB pSrc, pSrc, srcStep, LSL #2
|
| omxVCM4P10_InterpolateLuma_s.s | 21 ;// [in] srcStep Reference frame step in byte
38 ;// srcStep or dstStep >= roi.width.
44 ;// srcStep and dstStep is multiple of 8.
78 srcStep RN 1
148 STM pArgs, {pSrc,srcStep,pDst,dstStep}
211 SUB pSrc, pSrc, srcStep, LSL #1
229 LDM pArgs, {pSrc, srcStep, pDst, dstStep}
230 SUB pSrc, pSrc, srcStep, LSL #1
236 MOV srcStep, #4
246 SUB pSrc, pSrc, srcStep, LSL #
[all...] |
| armVCM4P10_InterpolateLuma_HalfDiagHorVer4x4_unsafe_s.s | 57 srcStep RN 1
108 M_STR srcStep, pSrcStep
113 LDR ValD, [pSrc, srcStep] ;// Load row 1 [d1 c1 b1 a1]
115 LDR ValH, [pSrc, srcStep] ;// Load [h1 g1 f1 e1]
117 LDRB Temp2, [pSrc, srcStep] ;// Load row 1 [l1 k1 j1 i1]
170 M_LDR srcStep, pSrcStep
205 ADD pSrc, pSrc, srcStep, LSL #1
218 MOV srcStep, #16
228 M_LDR ValCA, [pSrc], srcStep ;// Load [0 c 0 a]
229 M_LDR ValDB, [pSrc], srcStep ;// Load [0 d 0 b
[all...] |
| armVCM4P10_InterpolateLuma_HalfDiagVerHor4x4_unsafe_s.s | 54 srcStep RN 1
133 M_LDR ValC, [pSrc], srcStep ;// Load [c3 c2 c1 c0]
134 M_LDR ValD, [pSrc], srcStep ;// Load [d3 d2 d1 d0]
135 M_LDR ValE, [pSrc], srcStep ;// Load [e3 e2 e1 e0]
136 SUB pSrc, pSrc, srcStep, LSL #2
147 LDR ValD, [pSrc, srcStep, LSL #1] ;// Load [d3 d2 d1 d0]
153 LDR ValF, [pSrc, srcStep, LSL #2] ;// Load [f3 f2 f1 f0]
154 M_LDR ValB, [pSrc], srcStep ;// Load [b3 b2 b1 b0]
161 SUB ValA, pSrc, srcStep, LSL #1
172 LDR ValG, [pSrc, srcStep, LSL #2] ;// Load [g3 g2 g1 g0
[all...] |
| armVCM4P10_InterpolateLuma_HalfVer4x4_unsafe_s.s | 47 srcStep RN 1
104 M_LDR ValC, [pSrc], srcStep ;// Load [c3 c2 c1 c0]
105 M_LDR ValD, [pSrc], srcStep ;// Load [d3 d2 d1 d0]
106 M_LDR ValE, [pSrc], srcStep ;// Load [e3 e2 e1 e0]
107 SUB pSrc, pSrc, srcStep, LSL #2
119 LDR ValD, [pSrc, srcStep, LSL #1] ;// Load [d3 d2 d1 d0]
126 LDR ValF, [pSrc, srcStep, LSL #2] ;// Load [f3 f2 f1 f0]
127 M_LDR ValB, [pSrc], srcStep ;// Load [b3 b2 b1 b0]
134 SUB ValA, pSrc, srcStep, LSL #1
147 LDR ValG, [pSrc, srcStep, LSL #2] ;// Load [g3 g2 g1 g0
[all...] |
| /frameworks/base/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src/ |
| armVCM4P10_InterpolateLuma_Copy_unsafe_s.s | 34 srcStep RN 1
62 M_LDR x0, [pSrc], srcStep
63 M_LDR x1, [pSrc], srcStep
65 M_LDR x2, [pSrc], srcStep
67 M_LDR x3, [pSrc], srcStep
74 M_LDR x0, [pSrc], srcStep
76 M_LDR x2, [pSrc], srcStep
83 M_LDR x0, [pSrc], srcStep
86 M_LDR x2, [pSrc], srcStep
97 M_LDR x0, [pSrc], srcStep
[all...] |
| armVCM4P10_InterpolateLuma_Align_unsafe_s.s | 27 srcStep RN 1
78 ADD pSrc, pSrc, srcStep
89 ADD pSrc, pSrc, srcStep
105 ADD pSrc, pSrc, srcStep
121 ADD pSrc, pSrc, srcStep
136 MOV srcStep, #12
178 M_LDR x0, [pSrc], srcStep
189 M_LDR x0, [pSrc], srcStep
202 M_LDR x0, [pSrc], srcStep
215 M_LDR x0, [pSrc], srcStep
[all...] |
| armVCM4P10_InterpolateLuma_HalfVer4x4_unsafe_s.s | 26 srcStep RN 1
73 VLD1 dSrc0, [pSrc], srcStep ;// [a0 a1 a2 a3 .. ]
74 ADD Temp, pSrc, srcStep, LSL #2
75 VLD1 dSrc1, [pSrc], srcStep ;// [b0 b1 b2 b3 .. ]
77 VLD1 dSrc5, [Temp], srcStep
79 VLD1 dSrc2, [pSrc], srcStep ;// [c0 c1 c2 c3 .. ]
81 VLD1 dSrc3, [pSrc], srcStep
83 VLD1 dSrc6, [Temp], srcStep ;// TeRi
85 VLD1 dSrc4, [pSrc], srcStep
86 VLD1 dSrc7, [Temp], srcStep ;// TeR
[all...] |
| armVCM4P10_InterpolateLuma_HalfDiagHorVer4x4_unsafe_s.s | 26 srcStep RN 1
97 VLD1 qSrc01, [pSrc], srcStep ;// [a0 a1 a2 a3 ..]
110 VLD1 qSrc01, [pSrc], srcStep ;// [a0 a1 a2 a3 ..]
124 VLD1 qSrc01, [pSrc], srcStep ;// [a0 a1 a2 a3 ..]
141 VLD1 qSrc01, [pSrc], srcStep ;// [a0 a1 a2 a3 ..]
158 VLD1 qSrc01, [pSrc], srcStep ;// [a0 a1 a2 a3 ..]
175 VLD1 qSrc01, [pSrc], srcStep ;// [a0 a1 a2 a3 ..]
192 VLD1 qSrc01, [pSrc], srcStep ;// [a0 a1 a2 a3 ..]
209 VLD1 qSrc01, [pSrc], srcStep ;// [a0 a1 a2 a3 ..]
226 VLD1 qSrc01, [pSrc], srcStep ;// [a0 a1 a2 a3 ..
[all...] |
| armVCM4P10_InterpolateLuma_HalfHor4x4_unsafe_s.s | 28 srcStep RN 1
89 VLD1 qSrcA01, [pSrc], srcStep ;// Load A register [a0 a1 a2 a3 ..]
93 ; VLD1 qSrcB01, [pSrc], srcStep ;// Load B register [a0 a1 a2 a3 ..]
101 VLD1 qSrcB01, [pSrc], srcStep ;// Load B register [a0 a1 a2 a3 ..]
102 ; VLD1 qSrcC01, [pSrc], srcStep ;// Load C register [a0 a1 a2 a3 ..]
119 VLD1 qSrcC01, [pSrc], srcStep ;// Load C register [a0 a1 a2 a3 ..]
120 ; VLD1 qSrcD01, [pSrc], srcStep ;// Load D register [a0 a1 a2 a3 ..]
138 VLD1 qSrcD01, [pSrc], srcStep ;// Load D register [a0 a1 a2 a3 ..]
|
| armVCM4P10_InterpolateLuma_HalfDiagVerHor4x4_unsafe_s.s | 25 srcStep RN 1
119 VLD1 qSrcA01, [pSrc], srcStep ;// [a0 a1 a2 a3 .. a15]
120 ADD r12, pSrc, srcStep, LSL #2
123 VLD1 qSrcF1011, [r12], srcStep
124 VLD1 qSrcB23, [pSrc], srcStep ;// [b0 b1 b2 b3 .. b15]
126 VLD1 qSrcG1213, [r12], srcStep
128 VLD1 qSrcC45, [pSrc], srcStep ;// [c0 c1 c2 c3 .. c15]
130 VLD1 qSrcD67, [pSrc], srcStep
132 VLD1 qSrcE89, [pSrc], srcStep
137 VLD1 qSrcH1415, [r12], srcStep
[all...] |
| omxVCM4P10_InterpolateLuma_s.s | 21 ;// [in] srcStep Reference frame step in byte
38 ;// srcStep or dstStep >= roi.width.
44 ;// srcStep and dstStep is multiple of 8.
68 srcStep RN 1
192 STM pArgs, {pSrc,srcStep,pDst,dstStep}
219 ADD Temp, pSrc, srcStep, LSL #1
220 VLD1 dSrc0, [pSrc], srcStep
221 VLD1 dSrc2, [Temp], srcStep
283 SUB pSrc, pSrc, srcStep, LSL #1
301 SUB pSrc, pSrc, srcStep, LSL #
[all...] |
| omxVCM4P10_PredictIntra_4x4_s.s | 59 srcStep RN 10
179 ADD srcStep, leftStep, leftStep
181 VLD1 {dLeftVal0[]},[pSrcLeft],srcStep ;// pSrcLeft[0*leftStep]
182 VLD1 {dLeftVal1[]},[pSrcTmp],srcStep ;// pSrcLeft[1*leftStep]
219 ADD srcStep, leftStep, leftStep
221 VLD1 {dLeftVal[0]},[pSrcLeft],srcStep ;// pSrcLeft[0*leftStep]
222 VLD1 {dLeftVal[1]},[pSrcTmp],srcStep ;// pSrcLeft[1*leftStep]
333 ADD srcStep, leftStep, leftStep
336 VLD1 {dLeft[6]},[pSrcLeft],srcStep ;// pSrcLeft[0*leftStep]
337 VLD1 {dLeft[5]},[pSrcTmp],srcStep ;// pSrcLeft[1*leftStep
[all...] |
| /frameworks/base/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/vc/m4p2/src/ |
| omxVCM4P2_MCReconBlock_s.s | 72 ;// M_LOAD_X $pSrc, $srcStep, $out0, $out1, $scratch, $offset
77 ;// $srcStep The stride on source
92 M_LOAD_X $pSrc, $srcStep, $out0, $out1, $scratch, $offset
95 ADD $pSrc, $pSrc, $srcStep
98 ADD $pSrc, $pSrc, $srcStep
115 ;// M_LOAD_XINT $pSrc, $srcStep, $offset, $word0, $word1, $word2, $word3
121 ;// $srcStep The stride on source
127 ;// $pSrc Incremented by $srcStep
155 M_LOAD_XINT $pSrc, $srcStep, $offset, $word0, $word1, $word2, $word3
161 ADD $pSrc, $pSrc, $srcStep
[all...] |
| /frameworks/base/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p2/src/ |
| omxVCM4P2_MCReconBlock_s.s | 50 VLD1 dRow0, [pSrc], srcStep
51 VLD1 dRow1, [pSrc], srcStep
52 VLD1 dRow2, [pSrc], srcStep
53 VLD1 dRow3, [pSrc], srcStep
54 VLD1 dRow4, [pSrc], srcStep
55 VLD1 dRow5, [pSrc], srcStep
56 VLD1 dRow6, [pSrc], srcStep
57 VLD1 dRow7, [pSrc], srcStep
97 VLD1 {dRow0, dRow0Shft}, [pSrc], srcStep
99 VLD1 {dRow1, dRow1Shft}, [pSrc], srcStep
[all...] |
