| /external/llvm/include/llvm/CodeGen/ |
| LinkAllCodegenComponents.h | 45 (void) llvm::createBURRListDAGScheduler(NULL, llvm::CodeGenOpt::Default);
46 (void) llvm::createTDRRListDAGScheduler(NULL, llvm::CodeGenOpt::Default);
47 (void) llvm::createSourceListDAGScheduler(NULL,llvm::CodeGenOpt::Default);
48 (void) llvm::createHybridListDAGScheduler(NULL,llvm::CodeGenOpt::Default);
49 (void) llvm::createTDListDAGScheduler(NULL, llvm::CodeGenOpt::Default);
50 (void) llvm::createFastDAGScheduler(NULL, llvm::CodeGenOpt::Default);
51 (void) llvm::createDefaultScheduler(NULL, llvm::CodeGenOpt::Default);
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| MachineFunctionAnalysis.h | 29 CodeGenOpt::Level OptLevel;
35 CodeGenOpt::Level OL = CodeGenOpt::Default);
39 CodeGenOpt::Level getOptLevel() const { return OptLevel; }
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| SchedulerRegistry.h | 37 CodeGenOpt::Level);
69 CodeGenOpt::Level OptLevel);
74 CodeGenOpt::Level OptLevel);
79 CodeGenOpt::Level OptLevel);
86 CodeGenOpt::Level);
93 CodeGenOpt::Level);
97 CodeGenOpt::Level OptLevel);
102 CodeGenOpt::Level OptLevel);
107 CodeGenOpt::Level OptLevel);
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| /external/llvm/lib/Target/Blackfin/ |
| Blackfin.h | 27 CodeGenOpt::Level OptLevel);
|
| /external/llvm/lib/Target/PTX/ |
| PTX.h | 41 CodeGenOpt::Level OptLevel);
44 CodeGenOpt::Level OptLevel);
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| /external/llvm/lib/Target/ |
| TargetSubtargetInfo.cpp | 26 CodeGenOpt::Level OptLevel,
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| /external/llvm/include/llvm/Target/ |
| TargetMachine.h | 58 namespace CodeGenOpt {
266 CodeGenOpt::Level,
279 CodeGenOpt::Level,
292 CodeGenOpt::Level,
310 bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level,
324 CodeGenOpt::Level,
335 CodeGenOpt::Level,
346 CodeGenOpt::Level OptLevel,
353 virtual bool addPreISel(PassManagerBase &, CodeGenOpt::Level) {
359 virtual bool addInstSelector(PassManagerBase &, CodeGenOpt::Level)
[all...] |
| /external/llvm/lib/CodeGen/ |
| Passes.cpp | 50 FunctionPass *llvm::createRegisterAllocator(CodeGenOpt::Level OptLevel) {
68 case CodeGenOpt::None:
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| /external/llvm/lib/Target/MSP430/ |
| MSP430TargetMachine.cpp | 40 CodeGenOpt::Level OptLevel) {
47 CodeGenOpt::Level OptLevel) {
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| MSP430.h | 41 CodeGenOpt::Level OptLevel);
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| MSP430TargetMachine.h | 63 virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
64 virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
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| /external/llvm/lib/Target/ARM/ |
| ARMTargetMachine.cpp | 119 CodeGenOpt::Level OptLevel) {
120 if (OptLevel != CodeGenOpt::None)
127 CodeGenOpt::Level OptLevel) {
133 CodeGenOpt::Level OptLevel) {
135 if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
137 if (OptLevel != CodeGenOpt::None && Subtarget.isCortexA9())
144 CodeGenOpt::Level OptLevel) {
146 if (OptLevel != CodeGenOpt::None) {
157 if (OptLevel != CodeGenOpt::None) {
168 CodeGenOpt::Level OptLevel)
[all...] |
| ARMTargetMachine.h | 52 virtual bool addPreISel(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
53 virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
54 virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
55 virtual bool addPreSched2(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
56 virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
57 virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
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| /external/llvm/lib/Target/Mips/ |
| MipsTargetMachine.cpp | 55 addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel)
65 addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel)
72 addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel) {
78 addPostRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel) {
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| MipsTargetMachine.h | 64 CodeGenOpt::Level OptLevel);
66 CodeGenOpt::Level OptLevel);
68 CodeGenOpt::Level OptLevel);
69 virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level);
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| /external/llvm/lib/Target/SystemZ/ |
| SystemZ.h | 49 CodeGenOpt::Level OptLevel);
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| /external/llvm/lib/Target/X86/ |
| X86TargetMachine.h | 73 virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
74 virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
75 virtual bool addPostRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
76 virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
77 virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
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| /external/llvm/lib/ExecutionEngine/MCJIT/ |
| MCJIT.h | 27 RTDyldMemoryManager *MemMgr, CodeGenOpt::Level OptLevel,
82 CodeGenOpt::Level OptLevel,
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| /external/llvm/lib/Target/Alpha/ |
| AlphaTargetMachine.cpp | 41 CodeGenOpt::Level OptLevel) {
46 CodeGenOpt::Level OptLevel) {
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| AlphaTargetMachine.h | 59 virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
60 virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
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| /external/llvm/lib/Target/CellSPU/ |
| SPUSubtarget.cpp | 51 CodeGenOpt::Level OptLevel,
65 return OptLevel >= CodeGenOpt::Default;
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| SPUTargetMachine.cpp | 51 CodeGenOpt::Level OptLevel) {
59 addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel)
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| SPUTargetMachine.h | 84 CodeGenOpt::Level OptLevel);
85 virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level);
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| /external/llvm/lib/Target/MBlaze/ |
| MBlazeSubtarget.cpp | 56 enablePostRAScheduler(CodeGenOpt::Level OptLevel,
62 return HasItin && OptLevel >= CodeGenOpt::Default;
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| MBlazeTargetMachine.h | 79 virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level Opt);
80 virtual bool addPreEmitPass(PassManagerBase &PM,CodeGenOpt::Level Opt);
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