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    Searched refs:DTLB (Results 1 - 9 of 9) sorted by null

  /external/oprofile/events/i386/westmere/
unit_masks 64 0x01 any DTLB load misses
65 0x02 walk_completed DTLB load miss page walks complete
66 0x04 walk_cycles DTLB load miss page walk cycles
67 0x10 stlb_hit DTLB second level hit
68 0x20 pde_miss DTLB load miss caused by low part of address
69 0x80 large_walk_completed DTLB load miss large page walks
71 0x01 any DTLB misses
72 0x02 walk_completed DTLB miss page walks
73 0x04 walk_cycles DTLB miss page walk cycles
74 0x10 stlb_hit DTLB first level misses but second level hi
    [all...]
events 15 event:0x08 counters:0,1,2,3 um:dtlb_load_misses minimum:200000 name:DTLB_LOAD_MISSES : DTLB load misses
17 event:0x0c counters:0,1,2,3 um:x01 minimum:200000 name:MEM_STORE_RETIRED : Retired stores that miss the DTLB (Precise Event)
35 event:0x49 counters:0,1,2,3 um:dtlb_misses minimum:200000 name:DTLB_MISSES : DTLB misses
70 event:0xcb counters:0,1,2,3 um:mem_load_retired minimum:200000 name:MEM_LOAD_RETIRED : Retired loads that miss the DTLB (Precise Event)
  /external/oprofile/events/i386/atom/
unit_masks 14 0x07 dtlb_miss Memory accesses that missed the DTLB
15 0x05 dtlb_miss_ld DTLB misses due to load operations
17 0x06 dtlb_miss_st DTLB misses due to store operations
99 0x04 dtlb_miss Retired loads that miss the DTLB (precise event)
events 16 event:0x08 counters:0,1 um:data_tlb_misses minimum:6000 name:DATA_TLB_MISSES : Memory accesses that missed the DTLB
  /external/oprofile/events/mips/5K/
events 20 event:0x8 counters:0 um:zero minimum:500 name:DTLB_MISSES : DTLB miss
  /external/oprofile/events/x86-64/family11h/
events 44 event:0x45 counters:0,1,2,3 um:zero minimum:500 name:L1_DTLB_MISS_AND_L2_DTLB_HIT : L1 DTLB misses and L2 DTLB hits
45 event:0x46 counters:0,1,2,3 um:zero minimum:500 name:L1_DTLB_AND_L2_DTLB_MISS : L1 and L2 DTLB misses
  /external/oprofile/events/x86-64/hammer/
events 44 event:0x45 counters:0,1,2,3 um:zero minimum:500 name:L1_DTLB_MISS_AND_L2_DTLB_HIT : L1 DTLB misses and L2 DTLB hits
45 event:0x46 counters:0,1,2,3 um:zero minimum:500 name:L1_DTLB_AND_L2_DTLB_MISS : L1 and L2 DTLB misses
  /external/oprofile/events/i386/nehalem/
unit_masks 27 0x20 pde_miss Number of DTLB cache load misses where the low part of the linear to physical address translation was missed
28 0x40 pdp_miss Number of DTLB cache load misses where the high part of the linear to physical address translation was missed
39 0x01 dtlb_miss The event counts the number of retired stores that missed the DTLB
157 0x10 stlb_hit Counts the number of DTLB first level misses that hit in the second level TLB
158 0x20 pde_miss Number of DTLB cache misses where the low part of the linear to physical address translation was missed
159 0x40 pdp_miss Number of DTLB misses where the high part of the linear to physical address translation was missed
303 0x80 dtlb_miss Counts the number of retired loads that missed the DTLB
events 24 event:0x08 counters:0,1,2,3 um:dtlb_load_misses minimum:6000 name:DTLB_LOAD_MISSES : Counts dtlb page walks
27 event:0x0C counters:0,1,2,3 um:mem_store_retired minimum:6000 name:MEM_STORE_RETIRED : The event counts the number of retired stores that missed the DTLB. The DTLB miss is not counted if the store operation causes a fault. Does not count prefetches. Counts both primary and secondary misses to the TLB

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