| /external/llvm/include/llvm/MC/ |
| MCInstrItineraries.h | 197 /// index DefIdx can be bypassed when it's read by an instruction of
199 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx,
203 if ((FirstDefIdx + DefIdx) >= LastDefIdx)
205 if (Forwardings[FirstDefIdx + DefIdx] == 0)
213 return Forwardings[FirstDefIdx + DefIdx] ==
220 int getOperandLatency(unsigned DefClass, unsigned DefIdx,
225 int DefCycle = getOperandCycle(DefClass, DefIdx);
235 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx))
|
| /external/llvm/lib/Target/ |
| TargetInstrInfo.cpp | 66 const MachineInstr *DefMI, unsigned DefIdx,
73 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
78 SDNode *DefNode, unsigned DefIdx,
88 return ItinData->getOperandCycle(DefClass, DefIdx);
90 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
115 unsigned DefIdx) const {
120 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGSDNodes.h | 125 unsigned DefIdx;
143 return DefIdx-1;
|
| ScheduleDAGSDNodes.cpp | 507 DefIdx = 0;
513 : SchedDAG(SD), Node(SU->getNode()), DefIdx(0), NodeNumDefs(0) {
521 for (;DefIdx < NodeNumDefs; ++DefIdx) {
522 if (!Node->hasAnyUseOfValue(DefIdx))
524 ValueType = Node->getValueType(DefIdx);
525 ++DefIdx;
587 unsigned DefIdx = Use->getOperand(OpIdx).getResNo();
591 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx);
|
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.h | 343 const MachineInstr *DefMI, unsigned DefIdx,
347 SDNode *DefNode, unsigned DefIdx,
353 unsigned DefIdx, unsigned DefAlign) const;
357 unsigned DefIdx, unsigned DefAlign) const;
368 unsigned DefIdx, unsigned DefAlign,
380 const MachineInstr *DefMI, unsigned DefIdx,
383 const MachineInstr *DefMI, unsigned DefIdx) const;
|
| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| LiveRangeEdit.cpp | 122 SlotIndex DefIdx;
124 DefIdx = lis.getInstructionIndex(RM.OrigMI);
126 DefIdx = RM.ParentVNI->def;
127 RM.OrigMI = lis.getInstructionFromIndex(DefIdx);
136 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx, lis))
|
| RegisterCoalescer.cpp | 535 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
536 assert(DefIdx != -1);
538 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
644 SlotIndex DefIdx = UseIdx.getDefIndex();
645 VNInfo *DVNI = IntB.getVNInfoAt(DefIdx);
648 DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI);
649 assert(DVNI->def == DefIdx);
862 SlotIndex DefIdx = li_->getInstructionIndex(DefMI).getDefIndex();
863 LiveInterval::iterator MLR = li.FindLiveRangeContaining(DefIdx);
864 if (DefIdx != MLR->valno->def
[all...] |
| ScheduleDAGInstrs.cpp | 599 int DefIdx = DefMI->findRegisterDefOperandIdx(Reg);
600 if (DefIdx != -1) {
601 const MachineOperand &MO = DefMI->getOperand(DefIdx);
603 DefIdx >= (int)DefMI->getDesc().getNumOperands()) {
610 DefIdx = DefMI->findRegisterDefOperandIdx(Reg, false, true, TRI);
624 int UseCycle = TII->getOperandLatency(InstrItins, DefMI, DefIdx,
633 Latency = InstrItins->getOperandCycle(DefClass, DefIdx);
|
| InlineSpiller.cpp | 697 SlotIndex DefIdx = Edit->rematerializeAt(*MI->getParent(), MI, NewLI.reg, RM,
699 DEBUG(dbgs() << "\tremat: " << DefIdx << '\t'
700 << *LIS.getInstructionFromIndex(DefIdx));
712 VNInfo *DefVNI = NewLI.getNextValue(DefIdx, 0, LIS.getVNInfoAllocator());
713 NewLI.addRange(LiveRange(DefIdx, UseIdx.getDefIndex(), DefVNI));
[all...] |
| MachineInstr.cpp | [all...] |
| MachineVerifier.cpp | 618 unsigned defIdx;
619 if (MI->isRegTiedToDefOperand(MONum, &defIdx)) {
621 unsigned DefReg = MI->getOperand(defIdx).getReg();
692 SlotIndex DefIdx = LiveInts->getInstructionIndex(MI).getDefIndex();
695 if (const VNInfo *VNI = LI.getVNInfoAt(DefIdx)) {
697 if (VNI->def != DefIdx && !MO->isEarlyClobber()) {
700 << DefIdx << " in " << LI << '\n';
704 *OS << DefIdx << " is not live in " << LI << '\n';
[all...] |
| MachineLICM.cpp | 178 bool HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx,
787 unsigned DefIdx, unsigned Reg) const {
806 if (TII->hasHighOperandLatency(InstrItins, MRI, &MI, DefIdx, UseMI, i))
[all...] |
| RegAllocFast.cpp | 692 unsigned DefIdx = 0;
693 if (!MI->isRegTiedToDefOperand(i, &DefIdx)) continue;
695 << DefIdx << ".\n");
[all...] |
| VirtRegRewriter.cpp | [all...] |
| LiveIntervalAnalysis.cpp | 526 int DefIdx = mi->findRegisterDefOperandIdx(interval.reg,false,false,tri_);
527 if (DefIdx != -1) {
528 if (mi->isRegTiedToUseOperand(DefIdx)) {
645 SlotIndex defIdx = getMBBStartIdx(MBB);
646 assert(getInstructionFromIndex(defIdx) == 0 &&
649 interval.getNextValue(defIdx, 0, VNInfoAllocator);
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | 634 const MachineInstr *DefMI, unsigned DefIdx,
638 SDNode *DefNode, unsigned DefIdx,
663 const MachineInstr *DefMI, unsigned DefIdx,
672 const MachineInstr *DefMI, unsigned DefIdx) const;
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.h | [all...] |
| X86InstrInfo.cpp | [all...] |
