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    Searched refs:IndexReg (Results 1 - 12 of 12) sorted by null

  /external/llvm/lib/Target/SystemZ/
SystemZInstrBuilder.h 45 unsigned IndexReg;
49 SystemZAddressMode() : BaseType(RegBase), IndexReg(0), Disp(0) {
98 return MIB.addImm(AM.Disp).addReg(AM.IndexReg);
SystemZISelDAGToDAG.cpp 47 SDValue IndexReg;
52 : BaseType(RegBase), IndexReg(), Disp(0), isRI(RI) {
68 errs() << "IndexReg ";
69 if (IndexReg.getNode() != 0) IndexReg.getNode()->dump();
232 if (AM.IndexReg.getNode() || AM.isRI) {
249 AM.IndexReg = Neg;
281 !AM.Base.Reg.getNode() && !AM.IndexReg.getNode()) {
283 AM.IndexReg = N.getNode()->getOperand(1);
322 if (AM.IndexReg.getNode() == 0 && !AM.isRI)
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  /external/llvm/lib/Target/X86/InstPrinter/
X86ATTInstPrinter.cpp 107 const MCOperand &IndexReg = MI->getOperand(Op+2);
119 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
126 if (IndexReg.getReg() || BaseReg.getReg()) {
131 if (IndexReg.getReg()) {
X86IntelInstPrinter.cpp 96 const MCOperand &IndexReg = MI->getOperand(Op+2);
114 if (IndexReg.getReg()) {
129 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
  /external/llvm/lib/Target/X86/
X86InstrBuilder.h 50 unsigned IndexReg;
56 : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(0), GVOpFlags(0) {
73 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false,
134 MIB.addImm(AM.Scale).addReg(AM.IndexReg);
X86MCCodeEmitter.cpp 161 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
164 (IndexReg.getReg() != 0 && X86::GR32RegClass.contains(IndexReg.getReg())))
243 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
249 assert(IndexReg.getReg() == 0 && "Invalid rip-relative address");
280 IndexReg.getReg() == 0 &&
319 assert(IndexReg.getReg() != X86::ESP &&
320 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
356 if (IndexReg.getReg())
357 IndexRegNo = GetX86RegNum(IndexReg);
    [all...]
X86ISelDAGToDAG.cpp 64 SDValue IndexReg;
76 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0),
86 return IndexReg.getNode() != 0 || Base_Reg.getNode() != 0;
113 << "IndexReg ";
114 if (IndexReg.getNode() != 0)
115 IndexReg.getNode()->dump();
237 Index = AM.IndexReg;
703 AM.Base_Reg = AM.IndexReg;
715 AM.IndexReg.getNode() == 0 &&
780 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1
    [all...]
X86CodeEmitter.cpp 469 const MachineOperand &IndexReg = MI.getOperand(Op+2);
476 assert(IndexReg.getReg() == 0 && Is64BitMode &&
497 IndexReg.getReg() == 0 &&
535 assert(IndexReg.getReg() != X86::ESP &&
536 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
569 if (IndexReg.getReg())
570 IndexRegNo = X86_MC::getX86RegNum(IndexReg.getReg());
577 if (IndexReg.getReg())
578 IndexRegNo = X86_MC::getX86RegNum(IndexReg.getReg());
    [all...]
X86FastISel.cpp 394 unsigned IndexReg = AM.IndexReg;
431 if (IndexReg == 0 &&
436 IndexReg = getRegForGEPIndex(Op).first;
437 if (IndexReg == 0)
450 AM.IndexReg = IndexReg;
480 (AM.Base.Reg == 0 && AM.IndexReg == 0)) {
499 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
561 if (AM.IndexReg == 0)
    [all...]
X86AsmPrinter.cpp 283 const MachineOperand &IndexReg = MI->getOperand(Op+2);
293 bool HasParenPart = IndexReg.getReg() || HasBaseReg;
309 assert(IndexReg.getReg() != X86::ESP &&
316 if (IndexReg.getReg()) {
X86ISelLowering.cpp     [all...]
  /external/llvm/lib/Target/X86/AsmParser/
X86AsmParser.cpp 132 unsigned IndexReg;
181 return Mem.IndexReg;
326 Res->Mem.IndexReg = 0;
333 unsigned BaseReg, unsigned IndexReg,
337 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
346 Res->Mem.IndexReg = IndexReg;
361 Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0);
370 Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0;
500 /// ParseMemOperand: segment: disp(basereg, indexreg, scale). The '%ds:' prefi
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