| /external/clang/test/PCH/ |
| cxx-reference.h | 3 typedef char (&LR);
8 char &lr = c; variable
10 LR &lrlr = c;
11 LR &&rrlr = c;
|
| /external/clang/lib/StaticAnalyzer/Checkers/ |
| PointerArithChecker.cpp | 43 const MemRegion *LR = LV.getAsRegion();
45 if (!LR || !RV.isConstant())
50 if (isa<VarRegion>(LR) || isa<CodeTextRegion>(LR) ||
51 isa<CompoundLiteralRegion>(LR)) {
|
| PointerSubChecker.cpp | 46 const MemRegion *LR = LV.getAsRegion();
49 if (!(LR && RR))
52 const MemRegion *BaseLR = LR->getBaseRegion();
|
| /packages/apps/Camera/jni/ |
| mosaic_renderer_jni.h | 20 const int LR = 0; // Low-resolution mode
|
| mosaic_renderer_jni.cpp | 59 // to the {0,gPreviewImageWidth[LR]} input image frame coordinate system before
326 gPreviewImageWidth[LR] = widthLR;
327 gPreviewImageHeight[LR] = heightLR;
332 gPreviewImage[LR] = ImageUtils::allocateImage(gPreviewImageWidth[LR],
333 gPreviewImageHeight[LR], 4);
334 ClearPreviewImage(LR);
412 ImageUtils::freeImage(gPreviewImage[LR]);
440 gSurfTexRenderer[LR].InitializeGLProgram();
442 gYVURenderer[LR].InitializeGLProgram()
[all...] |
| feature_mos_jni.cpp | 53 // Variables to keep track of the mosaic computation progress for both LR & HR.
104 if(tWidth[LR]>180)
105 quarter_res[LR] = true;
282 tWidth[LR] = int(width / H2L_FACTOR);
283 tHeight[LR] = int(height / H2L_FACTOR);
287 tImage[LR][i] = ImageUtils::allocateImage(tWidth[LR], tHeight[LR],
293 AllocateTextureMemory(tWidth[HR], tHeight[HR], tWidth[LR], tHeight[LR]);
[all...] |
| /frameworks/base/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/vc/m4p2/src/ |
| armVCM4P2_DecodeVLCZigzag_AC_unsafe_s.s | 92 LR RN 14
112 M_STR LR,pLinkRegister ;// Store Link Register on Stack
114 MOV LR,#0
118 STM pDst!,{temp2,temp1,Last,LR}
120 STM pDst!,{temp2,temp1,Last,LR}
122 STM pDst!,{temp2,temp1,Last,LR}
124 STM pDst!,{temp2,temp1,Last,LR}
126 STM pDst!,{temp2,temp1,Last,LR}
128 STM pDst!,{temp2,temp1,Last,LR}
130 STM pDst!,{temp2,temp1,Last,LR}
[all...] |
| /frameworks/base/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p2/src/ |
| armVCM4P2_DecodeVLCZigzag_AC_unsafe_s.s | 92 LR RN 14
112 M_STR LR,pLinkRegister ;// Store Link Register on Stack
114 MOV LR,#0
118 STM pDst!,{temp2,temp1,Last,LR}
120 STM pDst!,{temp2,temp1,Last,LR}
122 STM pDst!,{temp2,temp1,Last,LR}
124 STM pDst!,{temp2,temp1,Last,LR}
126 STM pDst!,{temp2,temp1,Last,LR}
128 STM pDst!,{temp2,temp1,Last,LR}
130 STM pDst!,{temp2,temp1,Last,LR}
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| LiveInterval.h | 172 bool operator<(const LiveRange &LR) const {
173 return start < LR.start || (start == LR.start && end < LR.end);
175 bool operator==(const LiveRange &LR) const {
176 return start == LR.start && end == LR.end;
188 raw_ostream& operator<<(raw_ostream& os, const LiveRange &LR);
191 inline bool operator<(SlotIndex V, const LiveRange &LR) {
192 return V < LR.start
[all...] |
| /external/llvm/lib/CodeGen/ |
| RegAllocFast.cpp | 212 void RAFast::addKillFlag(const LiveReg &LR) {
213 if (!LR.LastUse) return;
214 MachineOperand &MO = LR.LastUse->getOperand(LR.LastOpNum);
215 if (MO.isUse() && !LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum)) {
216 if (MO.getReg() == LR.PhysReg)
219 LR.LastUse->addRegisterKilled(LR.PhysReg, TRI, true);
226 const LiveReg &LR = LRI->second
[all...] |
| LiveInterval.cpp | 249 LiveInterval::addRangeFrom(LiveRange LR, iterator From) {
250 SlotIndex Start = LR.start, End = LR.end;
254 // another interval, just extend that interval to contain the range of LR.
257 if (LR.valno == B->valno) {
274 if (LR.valno == it->valno) {
278 // If LR is a complete superset of an interval, we may need to grow its
294 return ranges.insert(it, LR);
531 iterator LR = I++;
532 if (LR->valno != V1) continue; // Not a V1 LiveRange
[all...] |
| LiveIntervalAnalysis.cpp | 335 LiveRange LR(defIndex, killIdx, ValNo);
336 interval.addRange(LR);
337 DEBUG(dbgs() << " +" << LR << "\n");
365 LiveRange LR(getMBBStartIdx(aliveBlock), getMBBEndIdx(aliveBlock), ValNo);
366 interval.addRange(LR);
367 DEBUG(dbgs() << " +" << LR);
386 LiveRange LR(Start, killIdx, ValNo);
387 interval.addRange(LR);
388 DEBUG(dbgs() << " +" << LR);
440 LiveRange LR(DefIndex, RedefIndex, ValNo)
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUFrameLowering.h | 27 std::pair<unsigned, int> LR[1];
69 //! Minimum frame size (enough to spill LR + SP)
|
| SPUTargetMachine.cpp | 31 return &LR[0];
|
| /external/llvm/lib/Target/XCore/ |
| XCoreFrameLowering.cpp | 129 MBB.addLiveIn(XCore::LR);
150 MachineLocation CSSrc(XCore::LR);
156 storeToStack(MBB, MBBI, XCore::LR, LRSpillOffset + FrameSize*4, dl, TII);
157 MBB.addLiveIn(XCore::LR);
163 MachineLocation CSSrc(XCore::LR);
256 loadFromStack(MBB, MBBI, XCore::LR, LRSpillOffset, dl, TII);
343 bool LRUsed = MF.getRegInfo().isPhysRegUsed(XCore::LR);
347 MF.getRegInfo().setPhysRegUnused(XCore::LR);
352 // A fixed offset of 0 allows us to save / restore LR using entsp / retsp.
|
| XCoreRegisterInfo.cpp | 41 : XCoreGenRegisterInfo(XCore::LR), TII(tii) {
80 XCore::R8, XCore::R9, XCore::R10, XCore::LR,
93 Reserved.set(XCore::LR);
|
| /external/llvm/lib/Target/XCore/MCTargetDesc/ |
| XCoreMCTargetDesc.cpp | 44 InitXCoreMCRegisterInfo(X, XCore::LR);
|
| /external/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.cpp | 59 : ARMGenRegisterInfo(ARM::LR), TII(tii), STI(sti),
67 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
78 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4,
410 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
415 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
422 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
427 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
434 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
439 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
446 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
[all...] |
| ARMFrameLowering.cpp | 161 case ARM::LR:
555 // Add the callee-saved register as live-in unless it's LR and
556 // @llvm.returnaddress is called. If LR is returned for
560 if (Reg == ARM::LR) {
629 if (Reg == ARM::LR && !isTailCall && !isVarArg && STI.hasV5TOps()) {
658 // If we adjusted the reg to PC from LR above, switch it back here. We
661 Regs[0] = ARM::LR;
[all...] |
| Thumb1FrameLowering.cpp | 92 case ARM::LR:
263 // to LR, and we can't pop the value directly to the PC since
265 // pop the old LR into R3 as a temporary.
270 // Epilogue for vararg functions: pop LR to R3 and branch off it.
303 // Add the callee-saved register as live-in unless it's LR and
304 // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress
306 if (Reg == ARM::LR) {
342 if (Reg == ARM::LR) {
|
| ARMBaseInfo.h | 152 /// ARM::LR, return the number that it corresponds to (e.g. 14).
172 case LR: case S14: case D14: case Q14: return 14;
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmLexer.cpp | 128 // r14 -> lr
135 .Case("r14", ARM::LR)
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCTargetDesc.cpp | 122 InitARMMCRegisterInfo(X, ARM::LR);
|
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCTargetDesc.cpp | 48 unsigned RA = isPPC64 ? PPC::LR8 : PPC::LR;
|
| /external/llvm/include/llvm/ADT/ |
| ImmutableSet.h | 498 TreeTy *LR = getRight(L);
500 if (getHeight(LL) >= getHeight(LR))
501 return createNode(LL, L, createNode(LR,V,R));
503 assert(!isEmpty(LR) && "LR cannot be empty because it has a height >= 1");
505 TreeTy *LRL = getLeft(LR);
506 TreeTy *LRR = getRight(LR);
508 return createNode(createNode(LL,L,LRL), LR, createNode(LRR,V,R));
[all...] |
