| /external/llvm/lib/CodeGen/ |
| RegisterClassInfo.cpp | 74 unsigned NumRegs = RC->getNumRegs();
77 RCI.Order.reset(new unsigned[NumRegs]);
96 RCI.NumRegs = N + CSRAlias.size();
97 assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
104 for (unsigned I = 0; I != RCI.NumRegs; ++I)
|
| RegisterClassInfo.h | 30 unsigned NumRegs;
33 RCInfo() : Tag(0), NumRegs(0) {}
35 return makeArrayRef(Order.get(), NumRegs);
80 return get(RC).NumRegs;
|
| RegAllocBase.h | 73 unsigned NumRegs;
76 LiveUnionArray(): NumRegs(0), Array(0) {}
79 unsigned numRegs() const { return NumRegs; }
86 assert(PhysReg < NumRegs && "physReg out of bounds");
|
| VirtRegMap.cpp | 93 unsigned NumRegs = MF->getRegInfo().getNumVirtRegs();
94 Virt2PhysMap.resize(NumRegs);
95 Virt2StackSlotMap.resize(NumRegs);
96 Virt2ReMatIdMap.resize(NumRegs);
97 Virt2SplitMap.resize(NumRegs);
98 Virt2SplitKillMap.resize(NumRegs);
99 ReMatMap.resize(NumRegs);
100 ImplicitDefed.resize(NumRegs);
227 unsigned NumRegs = TRI->getNumRegs();
229 UnusedRegs.resize(NumRegs);
[all...] |
| RegAllocBasic.cpp | 187 unionVRegs(new LiveVirtRegBitSet[PhysReg2LiveUnion.numRegs()]);
190 for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) {
224 NumRegs = NRegs;
239 const unsigned NumRegs = TRI->getNumRegs();
240 if (NumRegs != PhysReg2LiveUnion.numRegs()) {
241 PhysReg2LiveUnion.init(UnionAllocator, NumRegs);
243 Queries.reset(new LiveIntervalUnion::Query[PhysReg2LiveUnion.numRegs()]);
250 for (unsigned r = 0; r != NumRegs; ++r)
253 NumRegs = 0
[all...] |
| LiveVariables.cpp | 487 unsigned NumRegs = TRI->getNumRegs();
488 PhysRegDef = new MachineInstr*[NumRegs];
489 PhysRegUse = new MachineInstr*[NumRegs];
491 std::fill(PhysRegDef, PhysRegDef + NumRegs, (MachineInstr*)0);
492 std::fill(PhysRegUse, PhysRegUse + NumRegs, (MachineInstr*)0);
612 for (unsigned i = 0; i != NumRegs; ++i)
616 std::fill(PhysRegDef, PhysRegDef + NumRegs, (MachineInstr*)0);
617 std::fill(PhysRegUse, PhysRegUse + NumRegs, (MachineInstr*)0);
|
| MachineLICM.cpp | 432 unsigned NumRegs = TRI->getNumRegs();
433 unsigned *PhysRegDefs = new unsigned[NumRegs];
434 std::fill(PhysRegDefs, PhysRegDefs + NumRegs, 0);
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCRegisterInfo.h | 56 unsigned NumRegs; // Number of entries in the array
69 NumRegs = NR;
109 assert(RegNo < NumRegs &&
166 return NumRegs;
|
| /external/llvm/include/llvm/CodeGen/ |
| CallingConvLower.h | 231 /// NumRegs if they are all allocated.
232 unsigned getFirstUnallocated(const unsigned *Regs, unsigned NumRegs) const {
233 for (unsigned i = 0; i != NumRegs; ++i)
236 return NumRegs;
259 unsigned AllocateReg(const unsigned *Regs, unsigned NumRegs) {
260 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);
261 if (FirstUnalloc == NumRegs)
272 unsigned NumRegs) {
273 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);
274 if (FirstUnalloc == NumRegs)
[all...] |
| FastISel.h | 313 void UpdateValueMap(const Value* I, unsigned Reg, unsigned NumRegs = 1);
|
| /external/llvm/lib/Target/X86/ |
| SSEDomainFix.cpp | 100 static const unsigned NumRegs = 16;
158 assert(X86::XMM15 == X86::XMM0+NumRegs-1 && "Unexpected sort");
160 return reg < NumRegs ? (int) reg : -1;
181 assert(unsigned(rx) < NumRegs && "Invalid index");
183 LiveRegs = new DomainValue*[NumRegs];
184 std::fill(LiveRegs, LiveRegs+NumRegs, (DomainValue*)0);
199 assert(unsigned(rx) < NumRegs && "Invalid index");
212 assert(unsigned(rx) < NumRegs && "Invalid index");
244 for (unsigned rx = 0; rx != NumRegs; ++rx)
263 for (unsigned rx = 0; rx != NumRegs; ++rx
[all...] |
| X86FastISel.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMExpandPseudoInsts.cpp | 59 unsigned Opc, bool IsExt, unsigned NumRegs);
102 unsigned char NumRegs; // D registers loaded or stored
410 unsigned NumRegs = TableEntry->NumRegs;
422 if (NumRegs > 2)
424 if (NumRegs > 3)
474 unsigned NumRegs = TableEntry->NumRegs;
494 if (NumRegs > 2)
496 if (NumRegs > 3
[all...] |
| Thumb1FrameLowering.cpp | 339 bool NumRegs = false;
351 NumRegs = true;
355 if (NumRegs)
|
| ARMBaseInstrInfo.cpp | [all...] |
| ARMBaseRegisterInfo.cpp | 246 unsigned NumRegs = SubIndices.size();
247 if (NumRegs == 8) {
258 } else if (NumRegs == 4) {
295 } else if (NumRegs == 2) {
[all...] |
| ARMLoadStoreOptimizer.cpp | 295 unsigned NumRegs = Regs.size();
296 if (NumRegs <= 1)
305 else if (Offset == -4 * (int)NumRegs + 4 && haveIBAndDA)
307 else if (Offset == -4 * (int)NumRegs && isNotVFP)
318 if (NumRegs <= 2)
325 NewBase = Regs[NumRegs-1].first;
357 for (unsigned i = 0; i != NumRegs; ++i)
[all...] |
| ARMMCCodeEmitter.cpp | [all...] |
| ARMCodeEmitter.cpp | [all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FunctionLoweringInfo.cpp | 228 unsigned NumRegs = TLI.getNumRegisters(Ty->getContext(), ValueVT);
229 for (unsigned i = 0; i != NumRegs; ++i) {
|
| SelectionDAGBuilder.cpp | 229 unsigned NumRegs =
232 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
233 NumParts = NumRegs; // Silence a compiler warning.
500 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
505 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
506 NumParts = NumRegs; // Silence a compiler warning.
586 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
588 for (unsigned i = 0; i != NumRegs; ++i)
591 Reg += NumRegs;
657 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT)
[all...] |
| FastISel.cpp | 238 void FastISel::UpdateValueMap(const Value *I, unsigned Reg, unsigned NumRegs) {
250 for (unsigned i = 0; i < NumRegs; i++)
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| LoopStrengthReduce.cpp | 657 unsigned NumRegs;
666 : NumRegs(0), AddRecCost(0), NumIVMuls(0), NumBaseAdds(0), ImmCost(0),
734 ++NumRegs;
802 NumRegs = ~0u;
812 if (NumRegs != Other.NumRegs)
813 return NumRegs < Other.NumRegs;
828 OS << NumRegs << " reg" << (NumRegs == 1 ? "" : "s")
[all...] |
| /external/v8/src/ |
| frames.h | 40 int NumRegs(RegList list);
|
