| /external/llvm/include/llvm/Analysis/ |
| ConstantsScanner.h | 28 unsigned OpIdx; // Operand index
33 assert(!InstI.atEnd() && OpIdx < InstI->getNumOperands() &&
35 return isa<Constant>(InstI->getOperand(OpIdx));
39 inline constant_iterator(const Function *F) : InstI(inst_begin(F)), OpIdx(0) {
47 : InstI(inst_end(F)), OpIdx(0) {
50 inline bool operator==(const _Self& x) const { return OpIdx == x.OpIdx &&
56 return cast<Constant>(InstI->getOperand(OpIdx));
61 ++OpIdx;
64 while (OpIdx < NumOperands && !isAtConstant())
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMMCCodeEmitter.cpp | 77 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
80 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
86 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
91 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
95 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
99 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
103 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
108 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
113 uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
118 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
[all...] |
| ARMCodeEmitter.cpp | 103 unsigned OpIdx);
156 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const {
157 return getMachineOpValue(MI, MI.getOperand(OpIdx));
247 uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx)
249 uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx)
289 uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx)
291 uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
293 uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
[all...] |
| ARMExpandPseudoInsts.cpp | 414 unsigned OpIdx = 0;
416 bool DstIsDead = MI.getOperand(OpIdx).isDead();
417 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
428 MIB.addOperand(MI.getOperand(OpIdx++));
431 MIB.addOperand(MI.getOperand(OpIdx++));
432 MIB.addOperand(MI.getOperand(OpIdx++));
435 MIB.addOperand(MI.getOperand(OpIdx++));
442 SrcOpIdx = OpIdx++;
445 MIB.addOperand(MI.getOperand(OpIdx++));
446 MIB.addOperand(MI.getOperand(OpIdx++))
[all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassemblerCore.cpp | 596 unsigned &OpIdx = NumOpsAdded;
598 OpIdx = 0;
617 ++OpIdx;
629 OpIdx += 3;
633 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) {
636 ++OpIdx;
700 unsigned &OpIdx = NumOpsAdded;
721 OpIdx = 0;
726 ++OpIdx;
[all...] |
| ThumbDisassemblerCore.h | 354 unsigned &OpIdx = NumOpsAdded;
356 OpIdx = 0;
371 ++OpIdx;
374 if (OpInfo[OpIdx].RegClass == ARM::CCRRegClassID) {
375 assert(OpInfo[OpIdx].isOptionalDef() && "Optional def operand expected");
377 ++OpIdx;
381 assert(OpIdx < NumOps && "More operands expected");
382 if (OpInfo[OpIdx].RegClass == ARM::tGPRRegClassID) {
387 ++OpIdx;
391 if (OpIdx == NumOps
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ProcessImplicitDefs.h | 34 unsigned OpIdx,
|
| /external/llvm/utils/TableGen/ |
| CodeEmitterGen.cpp | 103 unsigned OpIdx;
104 if (CGI.Operands.hasOperandNamed(VarName, OpIdx)) {
106 OpIdx = CGI.Operands[OpIdx].MIOperandNo;
107 assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) &&
114 OpIdx = NumberedOp++;
117 std::pair<unsigned, unsigned> SO = CGI.Operands.getSubOperandNumber(OpIdx);
128 " op = " + EncoderMethodName + "(MI, " + utostr(OpIdx);
135 " op = getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) + ")";
|
| CodeGenInstruction.cpp | 135 unsigned OpIdx;
136 if (hasOperandNamed(Name, OpIdx)) return OpIdx;
142 /// given name. If so, return true and set OpIdx to the index of the
144 bool CGIOperandList::hasOperandNamed(StringRef Name, unsigned &OpIdx) const {
148 OpIdx = i;
171 unsigned OpIdx = getOperandNamed(OpName);
175 if (OperandList[OpIdx].MINumOperands > 1 && !AllowWholeOp &&
181 return std::make_pair(OpIdx, 0U);
185 DagInit *MIOpInfo = OperandList[OpIdx].MIOperandInfo
[all...] |
| CodeGenInstruction.h | 159 /// given name. If so, return true and set OpIdx to the index of the
161 bool hasOperandNamed(StringRef Name, unsigned &OpIdx) const;
|
| /external/llvm/lib/CodeGen/ |
| ProcessImplicitDefs.cpp | 49 unsigned Reg, unsigned OpIdx,
51 switch(OpIdx) {
257 unsigned OpIdx = Ops[j];
258 RMI->RemoveOperand(OpIdx-j);
|
| DwarfEHPrepare.cpp | 188 unsigned OpIdx = Sel->getNumArgOperands() - 1;
189 GlobalVariable *GV = dyn_cast<GlobalVariable>(Sel->getArgOperand(OpIdx));
191 Sel->setArgOperand(OpIdx, EHCatchAllValue->getInitializer());
|
| MachineInstr.cpp | [all...] |
| LiveIntervalAnalysis.cpp | [all...] |
| RegisterCoalescer.cpp | 600 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false);
601 NewMI->getOperand(OpIdx).setIsKill();
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGSDNodes.h | 104 unsigned OpIdx, SDep& dep) const;
|
| ScheduleDAGSDNodes.cpp | 579 unsigned OpIdx, SDep& dep) const{
587 unsigned DefIdx = Use->getOperand(OpIdx).getResNo();
590 OpIdx += TII->get(Use->getMachineOpcode()).getNumDefs();
591 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx);
|
| LegalizeVectorTypes.cpp | [all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeMCCodeEmitter.cpp | 49 unsigned getMachineOpValue(const MCInst &MI, unsigned OpIdx) const {
50 return getMachineOpValue(MI, MI.getOperand(OpIdx));
|
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
