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  /prebuilt/linux-x86/toolchain/i686-linux-glibc2.7-4.4.3/sysroot/usr/include/sys/
reg.h 35 # define R10 7
  /bionic/libc/kernel/arch-x86/asm/
ptrace-abi.h 47 #define R10 56
  /development/ndk/platforms/android-9/arch-x86/include/asm/
ptrace-abi.h 47 #define R10 56
  /external/kernel-headers/original/asm-x86/
ptrace-abi.h 36 #define R10 56
  /prebuilt/linux-x86/toolchain/i686-linux-glibc2.7-4.4.3/sysroot/usr/include/asm/
ptrace-abi.h 36 #define R10 56
  /prebuilt/ndk/android-ndk-r4/platforms/android-5/arch-x86/usr/include/asm/
ptrace-abi.h 47 #define R10 56
  /prebuilt/ndk/android-ndk-r4/platforms/android-8/arch-x86/usr/include/asm/
ptrace-abi.h 47 #define R10 56
  /prebuilt/ndk/android-ndk-r6/platforms/android-9/arch-x86/usr/include/asm/
ptrace-abi.h 47 #define R10 56
  /external/llvm/lib/Target/XCore/
XCoreFrameLowering.cpp 170 // Save R10 to the stack.
172 storeToStack(MBB, MBBI, XCore::R10, FPSpillOffset + FrameSize*4, dl, TII);
173 // R10 is live-in. It is killed at the spill.
174 MBB.addLiveIn(XCore::R10);
179 MachineLocation CSSrc(XCore::R10);
183 unsigned FramePtr = XCore::R10;
224 unsigned FramePtr = XCore::R10;
247 // Restore R10
250 loadFromStack(MBB, MBBI, XCore::R10, FPSpillOffset, dl, TII);
XCoreRegisterInfo.cpp 80 XCore::R8, XCore::R9, XCore::R10, XCore::LR,
95 Reserved.set(XCore::R10);
326 return TFI->hasFP(MF) ? XCore::R10 : XCore::SP;
  /external/llvm/lib/Target/ARM/
ARMBaseRegisterInfo.h 58 case R8: case R9: case R10: case R11:
69 case R8: case R9: case R10: case R11:
ARMBaseRegisterInfo.cpp 67 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
79 ARM::R11, ARM::R10, ARM::R8,
409 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
416 ARM::R8, ARM::R10
421 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10,
428 ARM::R8, ARM::R10
434 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
439 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
445 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10,
452 ARM::R10
    [all...]
ARMBaseInfo.h 168 case R10: case S10: case D10: case Q10: return 10;
Thumb1FrameLowering.cpp 100 case ARM::R10:
  /frameworks/base/media/libstagefright/codecs/aacdec/
esc_iquant_scaling.cpp 460 Int32 R12, R11, R10, R9;
470 MOV R10, #0x0
474 STMCSIA temp!, {R12, R11, R10, R9}
475 STMCSIA temp!, {R12, R11, R10, R9}
480 STMCSIA temp!, {R12, R11, R10, R9}
  /external/valgrind/main/VEX/auxprogs/
genoffsets.c 109 GENOFFSET(AMD64,amd64,R10);
  /external/llvm/lib/Target/MBlaze/
MBlazeRegisterInfo.cpp 62 case MBlaze::R10 : return 10;
127 case 10 : return MBlaze::R10;
  /external/valgrind/main/coregrind/m_sigframe/
sigframe-arm-linux.c 137 SC2(r10,R10);
310 REST(r10,R10);
sigframe-amd64-linux.c 346 SC2(r10,R10);
579 tst->arch.vex.guest_R10 = sc->r10;
  /external/llvm/lib/Target/X86/
X86RegisterInfo.cpp 99 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
409 X86::R8, X86::R9, X86::R10, X86::R11,
678 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
715 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
751 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
787 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
788 return X86::R10;
  /external/llvm/lib/Target/X86/Disassembler/
X86DisassemblerDecoder.h 171 ENTRY(R10) \
189 ENTRY(R10) \
  /external/llvm/lib/Target/X86/MCTargetDesc/
X86MCTargetDesc.cpp 146 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
223 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
  /system/core/libpixelflinger/codeflinger/
ARMAssemblerInterface.h 50 R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15,
58 LIST(R7), LIST(R8), LIST(R9), LIST(R10), LIST(R11), LIST(R12),
  /external/llvm/lib/Target/Alpha/
AlphaRegisterInfo.cpp 60 Alpha::R9, Alpha::R10,
  /external/llvm/lib/Target/CellSPU/
SPURegisterInfo.cpp 64 case SPU::R10: return 10;

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