| /bionic/libc/kernel/arch-x86/asm/ |
| ptrace-abi.h | 46 #define R11 48
62 #define ARGOFFSET R11
|
| /development/ndk/platforms/android-9/arch-x86/include/asm/ |
| ptrace-abi.h | 46 #define R11 48
62 #define ARGOFFSET R11
|
| /external/kernel-headers/original/asm-x86/ |
| ptrace-abi.h | 35 #define R11 48
52 #define ARGOFFSET R11
|
| /prebuilt/linux-x86/toolchain/i686-linux-glibc2.7-4.4.3/sysroot/usr/include/asm/ |
| ptrace-abi.h | 35 #define R11 48
52 #define ARGOFFSET R11
|
| /prebuilt/ndk/android-ndk-r4/platforms/android-5/arch-x86/usr/include/asm/ |
| ptrace-abi.h | 46 #define R11 48
62 #define ARGOFFSET R11
|
| /prebuilt/ndk/android-ndk-r4/platforms/android-8/arch-x86/usr/include/asm/ |
| ptrace-abi.h | 46 #define R11 48
62 #define ARGOFFSET R11
|
| /prebuilt/ndk/android-ndk-r6/platforms/android-9/arch-x86/usr/include/asm/ |
| ptrace-abi.h | 46 #define R11 48
62 #define ARGOFFSET R11
|
| /prebuilt/linux-x86/toolchain/i686-linux-glibc2.7-4.4.3/sysroot/usr/include/sys/ |
| reg.h | 34 # define R11 6
|
| /frameworks/base/media/libstagefright/codecs/aacdec/ |
| esc_iquant_scaling.cpp | 460 Int32 R12, R11, R10, R9;
469 MOV R11, #0x0
474 STMCSIA temp!, {R12, R11, R10, R9}
475 STMCSIA temp!, {R12, R11, R10, R9}
480 STMCSIA temp!, {R12, R11, R10, R9}
481 STMMIIA temp!, {R12, R11}
|
| /external/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.h | 58 case R8: case R9: case R10: case R11:
69 case R8: case R9: case R10: case R11:
|
| ARMBaseRegisterInfo.cpp | 60 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
67 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
79 ARM::R11, ARM::R10, ARM::R8,
127 case ARM::R11:
411 ARM::R9, ARM::R11
414 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
423 ARM::R9, ARM::R11
426 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11,
431 // FP is R11, R9 is available.
447 ARM::R11
[all...] |
| ARMBaseInfo.h | 169 case R11: case S11: case D11: case Q11: return 11;
|
| Thumb1FrameLowering.cpp | 101 case ARM::R11:
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeFrameLowering.cpp | 249 // Build the prologue SWI for R3 - R12 if needed. Note that R11 must
252 if (!MRI.isPhysRegUsed(r) && !(isIntr && r == MBlaze::R11)) continue;
274 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::MFS), MBlaze::R11)
276 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::SWI), MBlaze::R11)
279 BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::LWI), MBlaze::R11)
282 .addReg(MBlaze::R11);
|
| MBlazeRegisterInfo.cpp | 63 case MBlaze::R11 : return 11;
128 case 11 : return MBlaze::R11;
|
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineAndOrXor.cpp | 598 Value *R11,*R12;
600 if (match(R1, m_And(m_Value(R11), m_Value(R12)))) {
601 if (R11 != 0 && (R11 == L11 || R11 == L12 || R11 == L21 || R11 == L22)) {
602 A = R11; D = R12; E = R2; ok = true;
606 A = R12; D = R11; E = R2; ok = true;
609 if (!ok && match(R2, m_And(m_Value(R11), m_Value(R12))))
[all...] |
| /external/valgrind/main/VEX/auxprogs/ |
| genoffsets.c | 110 GENOFFSET(AMD64,amd64,R11);
|
| /external/valgrind/main/coregrind/m_sigframe/ |
| sigframe-arm-linux.c | 138 SC2(fp,R11);
311 REST(fp,R11);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 345 // we use R11, which we know cannot be used in the prolog/epilog. This is
347 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11));
349 .addReg(PPC::R11,
361 // we use R11, which we know cannot be used in the prolog/epilog. This is
508 PPC::R11), FrameIdx));
509 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11));
517 PPC::R11), FrameIdx));
518 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::R11));
541 // rlwinm r11, r11, 32-ShiftBits, 0, 31
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86RegisterInfo.cpp | 100 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
409 X86::R8, X86::R9, X86::R10, X86::R11,
680 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
717 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
753 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
789 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
790 return X86::R11;
|
| /external/llvm/lib/Target/X86/Disassembler/ |
| X86DisassemblerDecoder.h | 172 ENTRY(R11) \
190 ENTRY(R11) \
|
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCTargetDesc.cpp | 148 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
224 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
|
| /system/core/libpixelflinger/codeflinger/ |
| ARMAssemblerInterface.h | 50 R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15,
58 LIST(R7), LIST(R8), LIST(R9), LIST(R10), LIST(R11), LIST(R12),
|
| /external/llvm/lib/Target/Alpha/ |
| AlphaRegisterInfo.cpp | 61 Alpha::R11, Alpha::R12,
|
| /external/llvm/lib/Target/CellSPU/ |
| SPURegisterInfo.cpp | 65 case SPU::R11: return 11;
|
