| /external/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.h | 42 case R4: case R5: case R6: case R7:
55 case R4: case R5: case R6: case R7:
|
| ARMBaseRegisterInfo.cpp | 68 ARM::R7, ARM::R6, ARM::R5, ARM::R4,
78 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4,
410 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
414 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
422 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
426 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11,
434 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
438 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
446 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
450 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11
[all...] |
| ARMBaseInfo.h | 163 case R5: case S5: case D5: case Q5: return 5;
|
| ARMFrameLowering.cpp | 158 case ARM::R5:
[all...] |
| Thumb1FrameLowering.cpp | 89 case ARM::R5:
|
| /external/oprofile/module/ia64/ |
| IA64entry.h | 51 .spillsp r4, SW(R4)+16+(off); .spillsp r5, SW(R5)+16+(off); \
|
| /external/valgrind/main/VEX/auxprogs/ |
| genoffsets.c | 153 GENOFFSET(ARM,arm,R5);
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeRegisterInfo.cpp | 57 case MBlaze::R5 : return 5;
122 case 5 : return MBlaze::R5;
|
| MBlazeFrameLowering.cpp | 188 case MBlaze::R5: FILoc = -4; break;
|
| MBlazeISelLowering.cpp | 659 MBlaze::R5, MBlaze::R6, MBlaze::R7,
[all...] |
| /external/valgrind/main/coregrind/m_sigframe/ |
| sigframe-arm-linux.c | 132 SC2(r5,R5);
305 REST(r5,R5);
|
| /system/core/libpixelflinger/codeflinger/ |
| ARMAssemblerInterface.h | 50 R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15,
57 LIST(R0), LIST(R1), LIST(R2), LIST(R3), LIST(R4), LIST(R5), LIST(R6),
|
| /external/llvm/lib/Target/CellSPU/ |
| SPURegisterInfo.cpp | 59 case SPU::R5: return 5;
|
| SPUISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 79 XCore::R4, XCore::R5, XCore::R6, XCore::R7,
|
| /external/llvm/lib/Target/Blackfin/ |
| BlackfinRegisterInfo.cpp | 46 R4, R5, R6, R7,
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 81 case R5 : case X5 : case F5 : case V5 : case CR5: case CR1GT: return 5;
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| PPCISelLowering.cpp | [all...] |
| /external/valgrind/main/memcheck/ |
| mc_machine.c | 704 if (o == GOF(R5) && sz == 4) return o;
[all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassemblerCore.cpp | 176 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R5;
[all...] |
