| /external/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.cpp | 60 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
68 ARM::R7, ARM::R6, ARM::R5, ARM::R4,
78 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4,
126 case ARM::R7:
410 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
414 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
419 // FP is R7, R9 is available.
434 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
439 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
446 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
[all...] |
| ARMBaseRegisterInfo.h | 36 /// isARMLowRegister - Returns true if the register is low register r0-r7.
42 case R4: case R5: case R6: case R7:
49 /// isARMArea1Register - Returns true if the register is a low register (r0-r7)
55 case R4: case R5: case R6: case R7:
59 // For darwin we want r7 and lr to be next to each other.
|
| ARMBaseInfo.h | 165 case R7: case S7: case D7: case Q7: return 7;
|
| ARMFrameLowering.cpp | 160 case ARM::R7:
191 // For Darwin, FP is R7, which has now been stored in spill area 1.
234 // Restore from fp only in ARM mode: e.g. sub sp, r7, #24
237 // mov sp, r7
358 // mov sp, r7
[all...] |
| Thumb1FrameLowering.cpp | 91 case ARM::R7:
|
| ARMAsmPrinter.cpp | [all...] |
| ARMISelLowering.cpp | [all...] |
| /external/oprofile/module/ia64/ |
| IA64entry.h | 52 .spillsp r6, SW(R6)+16+(off); .spillsp r7, SW(R7)+16+(off); \
|
| /external/valgrind/main/VEX/auxprogs/ |
| genoffsets.c | 154 GENOFFSET(ARM,arm,R7);
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeRegisterInfo.cpp | 59 case MBlaze::R7 : return 7;
124 case 7 : return MBlaze::R7;
|
| MBlazeFrameLowering.cpp | 190 case MBlaze::R7: FILoc = -12; break;
|
| MBlazeISelLowering.cpp | 659 MBlaze::R5, MBlaze::R6, MBlaze::R7,
[all...] |
| /external/valgrind/main/coregrind/m_sigframe/ |
| sigframe-arm-linux.c | 134 SC2(r7,R7);
307 REST(r7,R7);
|
| /system/core/libpixelflinger/codeflinger/ |
| ARMAssemblerInterface.h | 50 R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15,
58 LIST(R7), LIST(R8), LIST(R9), LIST(R10), LIST(R11), LIST(R12),
|
| /external/llvm/lib/Target/CellSPU/ |
| SPURegisterInfo.cpp | 61 case SPU::R7: return 7;
|
| SPUISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 79 XCore::R4, XCore::R5, XCore::R6, XCore::R7,
|
| /external/llvm/lib/Target/Blackfin/ |
| BlackfinRegisterInfo.cpp | 46 R4, R5, R6, R7,
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 83 case R7 : case X7 : case F7 : case V7 : case CR7: case CR1UN: return 7;
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| PPCISelLowering.cpp | [all...] |
| /external/valgrind/main/memcheck/ |
| mc_machine.c | 706 if (o == GOF(R7) && sz == 4) return o;
[all...] |
| /external/chromium/third_party/libjingle/source/talk/session/phone/testdata/ |
| video.rtpdump | [all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassemblerCore.cpp | 196 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R7;
[all...] |
