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  /external/webkit/Source/JavaScriptCore/assembler/
MacroAssemblerARM.cpp 79 m_assembler.add_r(ARMRegisters::S0, address.base, op2);
80 m_assembler.ldrh_u(dest, ARMRegisters::S0, ARMAssembler::getOp2Byte(address.offset));
81 m_assembler.ldrh_u(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::getOp2Byte(address.offset + 0x2));
83 m_assembler.add_r(ARMRegisters::S0, address.base, op2);
84 m_assembler.ldrh_d(dest, ARMRegisters::S0, ARMAssembler::getOp2Byte(-address.offset));
85 m_assembler.ldrh_d(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::getOp2Byte(-address.offset - 0x2));
87 m_assembler.ldr_un_imm(ARMRegisters::S0, address.offset);
88 m_assembler.add_r(ARMRegisters::S0, ARMRegisters::S0, op2)
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ARMAssembler.cpp 272 add_r(ARMRegisters::S0, base, OP2_IMM | (offset >> 12) | (10 << 8));
273 dtr_u(isLoad, srcDst, ARMRegisters::S0, (offset & 0xfff) | transferFlag);
275 moveImm(offset, ARMRegisters::S0);
276 dtr_ur(isLoad, srcDst, base, ARMRegisters::S0 | transferFlag);
283 sub_r(ARMRegisters::S0, base, OP2_IMM | (offset >> 12) | (10 << 8));
284 dtr_d(isLoad, srcDst, ARMRegisters::S0, (offset & 0xfff) | transferFlag);
286 moveImm(offset, ARMRegisters::S0);
287 dtr_dr(isLoad, srcDst, base, ARMRegisters::S0 | transferFlag);
300 add_r(ARMRegisters::S0, base, op2);
301 dtr_u(isLoad, srcDst, ARMRegisters::S0, offset)
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MacroAssemblerARM.h 98 m_assembler.adds_r(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
114 ARMWord w = m_assembler.getImm(imm.m_value, ARMRegisters::S0, true);
125 m_assembler.and_r(ARMRegisters::S0, shift_amount, w);
127 m_assembler.movs_r(dest, m_assembler.lsl_r(dest, ARMRegisters::S0));
138 move(src, ARMRegisters::S0);
139 src = ARMRegisters::S0;
146 move(imm, ARMRegisters::S0);
147 m_assembler.muls_r(dest, src, ARMRegisters::S0);
167 m_assembler.orrs_r(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
174 m_assembler.and_r(ARMRegisters::S0, shift_amount, w)
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ARMAssembler.h 43 r3, S0 = r3,
612 dtr_dr(true, ARMRegisters::S0, ARMRegisters::S0, ARMRegisters::S0);
  /external/clang/test/SemaCXX/
type-definition-in-specifier.cpp 3 struct S0;
11 struct S0 { int x; };
alias-template.cpp 56 template<typename...T> struct S0 {
  /external/llvm/include/llvm/ADT/
StringSwitch.h 85 StringSwitch& Cases(const char (&S0)[N0], const char (&S1)[N1],
87 return Case(S0, Value).Case(S1, Value);
91 StringSwitch& Cases(const char (&S0)[N0], const char (&S1)[N1],
93 return Case(S0, Value).Case(S1, Value).Case(S2, Value);
97 StringSwitch& Cases(const char (&S0)[N0], const char (&S1)[N1],
100 return Case(S0, Value).Case(S1, Value).Case(S2, Value).Case(S3, Value);
104 StringSwitch& Cases(const char (&S0)[N0], const char (&S1)[N1],
107 return Case(S0, Value).Case(S1, Value).Case(S2, Value).Case(S3, Value)
  /external/clang/test/ASTMerge/Inputs/
struct1.c 5 struct S0 {
10 struct S0 x0;
struct2.c 2 struct S0 {
7 struct S0 x0;
  /external/clang/test/CXX/dcl.dcl/basic.namespace/namespace.def/namespace.memdef/
p3.cpp 10 struct S0 {
16 F0 f0() { return S0().member_func(); }
  /external/skia/bench/
ScalarBench.cpp 93 static SkBenchmark* S0(void* p) { return new FloatComparisonBench(p); }
96 static BenchRegistry gReg0(S0);
  /external/clang/test/CXX/temp/temp.arg/temp.arg.nontype/
p5.cpp 81 template <int& N> struct S0 { }; // expected-note 3 {{template parameter is declared here}}
90 S0<i> s0; local
91 S0<ci> s0c; // expected-error{{reference binding of non-type template parameter of type 'int &' to template argument of type 'const int' ignores qualifiers}}
92 S0<vi> s0v; // expected-error{{reference binding of non-type template parameter of type 'int &' to template argument of type 'volatile int' ignores qualifiers}}
93 S0<cvi> s0cv; // expected-error{{reference binding of non-type template parameter of type 'int &' to template argument of type 'const volatile int' ignores qualifiers}}
  /frameworks/base/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/api/
armCOMM_BitDec_s.h 487 ;// $S0 - The number of bits to look up for the first step
488 ;// 1<=$S0<=8
490 ;// step 1<=$S1<=$S0.
506 M_BD_VLD $Symbol, $T1, $T2, $pVLDTable, $S0, $S1
507 ASSERT (1<=$S0):LAND:($S0<=8)
508 ASSERT (1<=$S1):LAND:($S1<=$S0)
513 MOVS $Symbol, #(2<<$S0)-2 ;// create mask
514 AND $Symbol, $Symbol, $T1, LSR #(31-$S0) ;// 2*(next $S0 bits
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  /frameworks/base/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/api/
armCOMM_BitDec_s.h 487 ;// $S0 - The number of bits to look up for the first step
488 ;// 1<=$S0<=8
490 ;// step 1<=$S1<=$S0.
506 M_BD_VLD $Symbol, $T1, $T2, $pVLDTable, $S0, $S1
507 ASSERT (1<=$S0):LAND:($S0<=8)
508 ASSERT (1<=$S1):LAND:($S1<=$S0)
513 MOVS $Symbol, #(2<<$S0)-2 ;// create mask
514 AND $Symbol, $Symbol, $T1, LSR #(31-$S0) ;// 2*(next $S0 bits
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  /external/llvm/unittests/Analysis/
ScalarEvolutionTest.cpp 43 const SCEV *S0 = SE.getSCEV(V0);
47 const SCEV *P0 = SE.getAddExpr(S0, S0);
  /external/clang/test/CodeGen/
x86_64-arguments.c 207 struct S0 { char f0[8]; char f2; char f3; char f4; };
208 void f30(struct S0 p_4) {
  /external/libgsm/src/
long_term.c 366 register float S0 = 0, S1 = 0, S2 = 0, S3 = 0, S4 = 0,
381 E = W * a; S0 += E; } else (a = lp[K])
407 if (S0 > L_max) { L_max = S0; Nc = lambda; }
532 register float S0 = 0, S1 = 0, S2 = 0, S3 = 0, S4 = 0,
547 E = W * a; S0 += E
573 if (S0 > L_max) { L_max = S0; Nc = lambda; }
746 register float S0 = 0, S1 = 0, S2 = 0, S3 = 0, S4 = 0,
761 E = W * a; S0 +=
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  /external/llvm/lib/Target/Mips/
MipsRegisterInfo.cpp 70 case Mips::S0 : case Mips::F16: case Mips::D8: return 16;
106 Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0
112 Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0
  /libcore/luni/src/test/java/libcore/java/lang/
ClassCastExceptionTest.java 157 A0, B0, C0, D0, E0, F0, G0, H0, I0, J0, K0, L0, M0, N0, O0, P0, Q0, R0, S0, T0, U0, V0, W0, X0, Y0, Z0,
162 A0, B0, C0, D0, E0, F0, G0, H0, I0, J0, K0, L0, M0, N0, O0, P0, Q0, R0, S0, T0, U0, V0, W0, X0, Y0, Z0,
  /external/bouncycastle/src/main/java/org/bouncycastle/crypto/engines/
BlowfishEngine.java 303 private final int[] S0, S1, S2, S3; // the s-boxes
312 S0 = new int[SBOX_SK];
396 return (((S0[(x >>> 24)] + S1[(x >>> 16) & 0xff])
441 System.arraycopy(KS0, 0, S0, 0, SBOX_SK);
499 processTable(P[P_SZ - 2], P[P_SZ - 1], S0);
500 processTable(S0[SBOX_SK - 2], S0[SBOX_SK - 1], S1);
  /external/llvm/lib/Target/ARM/
ARMBaseInfo.h 158 case R0: case S0: case D0: case Q0: return 0;
ARMAsmPrinter.cpp 182 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
183 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
188 unsigned SReg = Reg - ARM::S0;
370 // that overlaps the 's' register. Also, s0 is an odd register, hence the
    [all...]
  /frameworks/base/media/libstagefright/codecs/avc/enc/src/
intra_est.cpp 734 int P0, Q0, R0, S0, P1, Q1, R1, P2, Q2;
1058 S0 = P_C + P_D + 1;
1064 R1 = (R0 + S0) >> 2;
1069 S0 >>= 1;
1074 temp = P0 | (Q0 << 8); //[P0 Q0 R0 S0]
1077 temp |= (S0 << 24); //[Q2 D P1 Q1]
1107 S0 = P_K + P_L + 1;
1111 R1 = (R0 + S0) >> 2;
1116 S0 >>= 1;
1123 temp |= (Q2 << 24); //[S0 R1 R0 Q1
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  /external/webkit/Source/JavaScriptCore/jit/
JSInterfaceJIT.h 122 static const RegisterID regS0 = ARMRegisters::S0;
149 static const RegisterID callFrameRegister = MIPSRegisters::s0;
  /external/chromium/crypto/third_party/nss/
sha512.cc 154 #define S0(x) (ROTR32(x, 2) ^ ROTR32(x,13) ^ ROTR32(x,22))
156 #define s0(x) (t1 = x, ROTR32(t1, 7) ^ ROTR32(t1,18) ^ SHR(t1, 3)) macro
206 #define INITW(t) W[t] = (s1(W[t-2]) + W[t-7] + s0(W[t-15]) + W[t-16])
289 h += S0(a) + Maj(a,b,c);
391 #undef s0 macro
393 #undef S0
535 #define S0(x) (ROTR64(x,28) ^ ROTR64(x,34) ^ ROTR64(x,39))
537 #define s0(x) (t1 = x, ROTR64(t1, 1) ^ ROTR64(t1, 8) ^ SHR(t1,7))
723 #define INITW(t) W[t] = (s1(W[t-2]) + W[t-7] + s0(W[t-15]) + W[t-16])
728 h += S0(a) + Maj(a,b,c);
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