| /external/llvm/lib/Target/PTX/ |
| PTXISelLowering.cpp | 78 // select_cc => setcc
95 // customise setcc to use bitwise logic if possible
97 setOperationAction(ISD::SETCC, MVT::i1, Custom);
116 case ISD::SETCC:
145 assert(Op.getValueType() == MVT::i1 && "SetCC type must be 1-bit integer");
163 return DAG.getNode(ISD::SETCC, dl, MVT::i1, Op0, Op1, Op2);
|
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 332 // SetCC operator - This evaluates to a true value iff the condition is
337 SETCC,
492 // compare, rather than as a combined SetCC node. The operands in order are
[all...] |
| SelectionDAG.h | 558 /// getSetCC - Helper function to make it easier to build SetCC's if you just
563 return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond));
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 50 /// SetCC - Operand 0 is condition code, and operand 1 is the flag
52 SETCC,
|
| MSP430ISelLowering.cpp | 114 setOperationAction(ISD::SETCC, MVT::i8, Custom);
115 setOperationAction(ISD::SETCC, MVT::i16, Custom);
187 case ISD::SETCC: return LowerSETCC(Op, DAG);
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 116 setOperationAction(ISD::SETCC, MVT::i32, Expand);
117 setOperationAction(ISD::SETCC, MVT::i64, Expand);
118 setOperationAction(ISD::SETCC, MVT::f32, Expand);
119 setOperationAction(ISD::SETCC, MVT::f64, Expand);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 323 Ops[i] = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(TmpEltVT),
|
| DAGCombiner.cpp | 494 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
495 // that selects between the values 1 and 0, making it equivalent to a setcc.
501 if (N.getOpcode() == ISD::SETCC) {
520 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
[all...] |
| LegalizeFloatTypes.cpp | 584 case ISD::SETCC: Res = SoftenFloatOp_SETCC(N); break;
604 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
611 assert((VT == MVT::f32 || VT == MVT::f64) && "Unsupported setcc type!");
668 default: assert(false && "Do not know how to soften this setcc!");
679 SDValue Tmp = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(RetVT),
682 NewLHS = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(RetVT), NewLHS,
[all...] |
| LegalizeVectorTypes.cpp | 62 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
244 // Turn it into a scalar SETCC.
245 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
268 // Turn it into a scalar SETCC.
269 SDValue Res = DAG.getNode(ISD::SETCC, DL, SVT, LHS, RHS, N->getOperand(2));
271 // VSETCC always returns a sign-extended value, while SETCC may not. The
272 // SETCC result type may not match the vector element type. Correct these.
274 // The SETCC result type is bigger than the vector element type.
275 // Ensure the SETCC result is sign-extended.
284 // The SETCC result type is smaller than the vector element type
[all...] |
| TargetLowering.cpp | [all...] |
| LegalizeDAG.cpp | 45 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
46 /// will attempt merge setcc and brc instructions into brcc's.
[all...] |
| LegalizeIntegerTypes.cpp | 67 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
470 assert(isTypeLegal(SVT) && "Illegal SetCC type!");
473 // Get the SETCC result using the canonical SETCC type.
474 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, SVT, N->getOperand(0),
480 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
726 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
759 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
[all...] |
| SelectionDAG.cpp | 224 /// 'op' is a valid SetCC operation.
244 default: llvm_unreachable("Illegal integer setcc operation!");
265 // Cannot fold a signed integer setcc with an unsigned integer setcc.
275 // Canonicalize illegal integer setcc's.
289 // Cannot fold a signed setcc with an unsigned setcc.
295 // Canonicalize illegal integer setcc's.
[all...] |
| /external/llvm/lib/Target/Alpha/ |
| AlphaISelDAGToDAG.cpp | 303 case ISD::SETCC:
|
| AlphaISelLowering.cpp | 128 setOperationAction(ISD::SETCC, MVT::f32, Promote);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 223 // X86 is weird, it always uses i8 for shift amounts and setcc results.
453 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
454 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
455 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
456 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
457 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
458 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
461 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
[all...] |
| X86ISelLowering.h | 89 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
91 SETCC,
93 // Same as SETCC except it's materialized with a sbb and the value is all
97 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
567 /// getSetCCResultType - Return the ISD::SETCC ValueType
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 312 setOperationAction(ISD::SETCC, MVT::i8, Legal);
313 setOperationAction(ISD::SETCC, MVT::i16, Legal);
314 setOperationAction(ISD::SETCC, MVT::i32, Legal);
315 setOperationAction(ISD::SETCC, MVT::i64, Legal);
316 setOperationAction(ISD::SETCC, MVT::f64, Custom);
497 // Return the Cell SPU's SETCC result type
501 // i8, i16 and i32 are valid SETCC result types
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 731 // Sparc has no select or setcc: expand to SELECT_CC.
735 setOperationAction(ISD::SETCC, MVT::i32, Expand);
736 setOperationAction(ISD::SETCC, MVT::f32, Expand);
737 setOperationAction(ISD::SETCC, MVT::f64, Expand);
[all...] |
| /external/llvm/lib/Target/Blackfin/ |
| BlackfinISelLowering.cpp | 75 setOperationAction(ISD::SETCC, MVT::i16, Promote);
138 // SETCC always sets the CC register. Technically that is an i1 register, but
|
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 75 // setcc operations results (slt, sgt, ...).
96 // Used by legalize types to correctly generate the setcc result.
97 // Without this, every float setcc comes with a AND/OR with the result,
100 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
183 setTargetDAGCombine(ISD::SETCC);
443 // Creates and returns an FPCmp node from a setcc node.
444 // Returns Op if setcc is not a floating point comparison.
446 // must be a SETCC node
447 if (Op.getOpcode() != ISD::SETCC)
508 case ISD::SETCC
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 60 // setcc operations results (slt, sgt, ...).
137 // Used by legalize types to correctly generate the setcc result.
138 // Without this, every float setcc comes with a AND/OR with the result,
141 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
361 // setcc r1, r2, r3
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 573 /// associated with the SetCC condition, and whether or not the field is
617 // We can codegen setcc op, imm very efficiently compared to a brcond.
619 // setcc op, 0
649 } else if (Imm == ~0U) { // setcc op, -1
819 case ISD::SETCC:
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 681 setOperationAction(ISD::SETCC, MVT::i32, Expand);
682 setOperationAction(ISD::SETCC, MVT::f32, Expand);
683 setOperationAction(ISD::SETCC, MVT::f64, Expand);
[all...] |
