| /external/libffi/src/mips/ |
| ffitarget.h | 128 # define SRL srl
135 # define SRL dsrl
|
| n32.S | 119 SRL t4, t6, 1*FFI_FLAG_BITS
132 SRL t4, t6, 2*FFI_FLAG_BITS
145 SRL t4, t6, 3*FFI_FLAG_BITS
158 SRL t4, t6, 4*FFI_FLAG_BITS
171 SRL t4, t6, 5*FFI_FLAG_BITS
184 SRL t4, t6, 6*FFI_FLAG_BITS
197 SRL t4, t6, 7*FFI_FLAG_BITS
219 SRL t6, 8*FFI_FLAG_BITS
|
| o32.S | 80 SRL t2, t0, 4 # shift our arg info
|
| /external/openssl/crypto/sha/asm/ |
| sha512-sparcv9.pl | 59 $SRL="srlx"; # shift right logical
85 $SRL="srl"; # shift right logical
222 $SRL $e,@Sigma1[0],$h !! $i
226 $SRL $e,@Sigma1[1],$tmp0
230 $SRL $e,@Sigma1[2],$tmp0
237 $SRL $a,@Sigma0[0],$h
242 $SRL $a,@Sigma0[1],$tmp0
246 $SRL $a,@Sigma0[2],$tmp0
276 srl $xi,@sigma0[0],$T1 !! Xupdate($i
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 153 case ISD::SRL:
265 // Make sure that the SINT_TO_FP and SRL instructions are available.
267 !TLI.isOperationLegalOrCustom(ISD::SRL, VT))
287 SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord);
|
| LegalizeIntegerTypes.cpp | 72 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
242 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
517 return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1));
617 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
738 case ISD::SRL:
[all...] |
| DAGCombiner.cpp | 838 else if (Opc == ISD::SRL)
[all...] |
| TargetLowering.cpp | [all...] |
| LegalizeDAG.cpp | 481 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
[all...] |
| FastISel.cpp | 900 return SelectBinaryOp(I, ISD::SRL);
[all...] |
| SelectionDAGBuilder.h | 476 void visitLShr(const User &I) { visitShift(I, ISD::SRL); }
|
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 317 SHL, SRA, SRL, ROTL, ROTR,
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 64 /// SHL, SRA, SRL - Non-constant shifts.
65 SHL, SRA, SRL
|
| MSP430ISelLowering.cpp | 99 setOperationAction(ISD::SRL, MVT::i8, Custom);
102 setOperationAction(ISD::SRL, MVT::i16, Custom);
182 case ISD::SRL:
609 case ISD::SRL:
610 return DAG.getNode(MSP430ISD::SRL, dl,
621 if (Opc == ISD::SRL && ShiftAmount) {
623 // srl A, 1 => clrc; rrc A
825 // FIXME: somewhere this is turned into a SRL, lower it MSP specific?
[all...] |
| /external/v8/src/mips/ |
| constants-mips.cc | 243 case SRL:
|
| constants-mips.h | 250 SRL = ((0 << 3) + 2),
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 351 } else if (Opcode == ISD::SRL) {
398 Op0.getOperand(0).getOpcode() == ISD::SRL) {
400 Op1.getOperand(0).getOpcode() != ISD::SRL) {
406 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
408 Op1.getOperand(0).getOpcode() != ISD::SRL) {
419 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
426 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) &&
[all...] |
| PPCISelLowering.h | 91 SRL, SRA, SHL,
|
| /external/llvm/lib/Target/ARM/ |
| ARMAddressingModes.h | 67 case ISD::SRL: return ARM_AM::lsr;
|
| ARMISelLowering.cpp | 126 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
499 setTargetDAGCombine(ISD::SRL);
551 setOperationAction(ISD::SRL, MVT::i64, Custom);
[all...] |
| /external/llvm/lib/Target/Alpha/ |
| AlphaISelLowering.cpp | 596 SDValue Lo_Neg = DAG.getNode(ISD::SRL, dl, MVT::i64, ShOpHi, ShAmt_Neg);
599 SDValue Hi_Pos = DAG.getNode(ISD::SRL, dl, MVT::i64, ShOpHi, ShAmt);
600 SDValue Lo_Pos = DAG.getNode(ISD::SRL, dl, MVT::i64, ShOpLo, ShAmt);
[all...] |
| AlphaISelDAGToDAG.cpp | 360 if (N->getOperand(0).getOpcode() == ISD::SRL &&
|
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 244 setOperationAction(ISD::SRL, MVT::i8, Custom);
249 setOperationAction(ISD::SRL, MVT::i64, Legal);
[all...] |
| SPUISelDAGToDAG.cpp | 233 //! Emit the instruction sequence for i64 srl
753 if ((Op0.getOpcode() == ISD::SRA || Op0.getOpcode() == ISD::SRL)
756 // Catch (truncate:i32 ([sra|srl]:i64 arg, c), where c >= 32
775 if (Op0.getOpcode() == ISD::SRL)
789 } else if (Opc == ISD::SRL) {
[all...] |
| /external/llvm/utils/TableGen/ |
| Record.cpp | 734 case SRL: {
744 case SRL: Result = (uint64_t)LHSv >> (uint64_t)RHSv; break;
769 case SRL: Result = "!srl"; break;
[all...] |
