| /external/v8/test/cctest/ |
| test-disasm-arm.cc | 111 COMPARE(and_(r2, r3, Operand(r4), SetCC),
118 COMPARE(eor(r4, r5, Operand(r7, LSL, 1), SetCC),
122 COMPARE(eor(r4, r5, Operand(r9, LSL, 3), SetCC, cs),
127 COMPARE(sub(r5, r6, Operand(r10, LSL, 30), SetCC, cc),
131 COMPARE(sub(r5, r6, Operand(r10, LSL, 16), SetCC, mi),
138 COMPARE(rsb(r6, r7, Operand(fp, LSR, 0), SetCC),
147 COMPARE(add(r7, r8, Operand(ip), SetCC),
149 COMPARE(add(r7, r8, Operand(ip, ASR, 31), SetCC, vs),
156 COMPARE(adc(r5, sp, Operand(ip), SetCC),
158 COMPARE(adc(r8, lr, Operand(ip, ASR, 31), SetCC, vc)
[all...] |
| /external/v8/src/arm/ |
| code-stubs-arm.cc | 321 __ and_(exponent, source_, Operand(HeapNumber::kSignMask), SetCC);
695 __ and_(dst2, scratch1, Operand(HeapNumber::kSignMask), SetCC);
697 __ rsb(scratch1, scratch1, Operand(0), SetCC, mi);
716 __ sub(scratch2, dst1, Operand(HeapNumber::kMantissaBitsInTopWord), SetCC);
[all...] |
| constants-arm.h | 274 SetCC = 1 << 20, // Set condition code.
|
| regexp-macro-assembler-arm.cc | 295 __ sub(r1, r1, r0, SetCC); // Length of capture.
398 __ sub(r1, r1, r0, SetCC); // Length to check.
636 __ sub(r0, sp, r0, SetCC);
689 __ sub(r2, r2, Operand(1), SetCC);
[all...] |
| macro-assembler-arm.cc | [all...] |
| stub-cache-arm.cc | [all...] |
| builtins-arm.cc | 342 __ and_(r3, r2, Operand(kIntptrSignBit | kSmiTagMask), SetCC);
697 __ sub(r4, r4, Operand(1), SetCC);
775 __ sub(r3, r3, Operand(r6), SetCC);
[all...] |
| lithium-codegen-arm.cc | 160 __ sub(r0, r0, Operand(1), SetCC);
845 __ rsb(dividend, dividend, Operand(0), SetCC);
956 __ sub(scratch2, left, scratch, SetCC);
[all...] |
| full-codegen-arm.cc | [all...] |
| macro-assembler-arm.h | [all...] |
| ic-arm.cc | [all...] |
| /external/v8/src/ia32/ |
| disasm-ia32.cc | 342 int SetCC(byte* data);
639 int DisassemblerIA32::SetCC(byte* data) {
991 data += SetCC(data);
[all...] |
| /external/v8/src/x64/ |
| disasm-x64.cc | 427 int SetCC(byte* data);
821 int DisassemblerX64::SetCC(byte* data) {
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | 494 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
495 // that selects between the values 1 and 0, making it equivalent to a setcc.
501 if (N.getOpcode() == ISD::SETCC) {
520 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
[all...] |
| LegalizeIntegerTypes.cpp | 67 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
470 assert(isTypeLegal(SVT) && "Illegal SetCC type!");
473 // Get the SETCC result using the canonical SETCC type.
474 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, SVT, N->getOperand(0),
480 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
726 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
759 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 223 // X86 is weird, it always uses i8 for shift amounts and setcc results.
453 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
454 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
455 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
456 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
457 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
458 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
461 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
[all...] |
