| /external/clang/lib/Lex/ |
| PPExpressions.cpp | 555 unsigned ShAmt = static_cast<unsigned>(RHS.Val.getLimitedValue());
557 Overflow = ShAmt >= LHS.Val.getBitWidth();
559 ShAmt = LHS.Val.getBitWidth()-1;
560 Res = LHS.Val << ShAmt;
562 Res = llvm::APSInt(LHS.Val.sshl_ov(ShAmt, Overflow), false);
568 unsigned ShAmt = static_cast<unsigned>(RHS.Val.getLimitedValue());
569 if (ShAmt >= LHS.getBitWidth())
570 Overflow = true, ShAmt = LHS.getBitWidth()-1;
571 Res = LHS.Val >> ShAmt;
|
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineShifts.cpp | 360 Constant *ShAmt = ConstantExpr::getZExt(Op1, TrOp->getType());
362 Value *NSh = Builder->CreateBinOp(I.getOpcode(), TrOp, ShAmt,I.getName());
630 unsigned ShAmt = Op1C->getZExtValue();
635 APInt::getHighBitsSet(Op1C->getBitWidth(), ShAmt))) {
642 ComputeNumSignBits(I.getOperand(0)) > ShAmt) {
669 unsigned ShAmt = Op1C->getZExtValue();
679 isPowerOf2_32(BitWidth) && Log2_32(BitWidth) == ShAmt) {
689 MaskedValueIsZero(Op0,APInt::getLowBitsSet(Op1C->getBitWidth(),ShAmt))){
709 unsigned ShAmt = Op1C->getZExtValue();
735 MaskedValueIsZero(Op0,APInt::getLowBitsSet(Op1C->getBitWidth(),ShAmt))){
[all...] |
| InstCombineCasts.cpp | [all...] |
| InstCombineCompares.cpp | [all...] |
| InstCombineAddSub.cpp | 135 Constant *ShAmt = ConstantInt::get(I.getType(), ExtendAmt);
136 Value *NewShl = Builder->CreateShl(XorLHS, ShAmt, "sext");
137 return BinaryOperator::CreateAShr(NewShl, ShAmt);
|
| InstCombineMulDivRem.cpp | 522 Value *ShAmt = llvm::ConstantInt::get(RHS->getType(),
524 return BinaryOperator::CreateExactAShr(Op0, ShAmt, I.getName());
|
| InstCombineAndOrXor.cpp | [all...] |
| InstructionCombining.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
| SelectionDAG.cpp | [all...] |
| SelectionDAGBuilder.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | 92 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
359 unsigned ShAmt) {
365 return ShOpcVal == ARM_AM::lsl && ShAmt == 2;
462 unsigned ShAmt = Log2_32(RHSC);
464 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
493 unsigned ShAmt = 0;
503 ShAmt = Sh->getZExtValue();
504 if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
507 ShAmt = 0;
524 ShAmt = Sh->getZExtValue()
[all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| ScalarReplAggregates.cpp | [all...] |
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 746 unsigned ShAmt = MO3.getImm();
747 if (ShAmt) {
748 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
749 O << ", lsl #" << ShAmt;
|
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Alpha/ |
| AlphaISelLowering.cpp | 587 SDValue ShAmt = Op.getOperand(2);
589 DAG.getConstant(64, MVT::i64), ShAmt);
592 // if 64 - shAmt <= 0
599 SDValue Hi_Pos = DAG.getNode(ISD::SRL, dl, MVT::i64, ShOpHi, ShAmt);
600 SDValue Lo_Pos = DAG.getNode(ISD::SRL, dl, MVT::i64, ShOpLo, ShAmt);
[all...] |
| /external/llvm/lib/VMCore/ |
| ConstantFold.cpp | 254 unsigned ShAmt = Amt->getZExtValue();
256 if ((ShAmt & 7) != 0)
258 ShAmt >>= 3;
261 if (ByteStart >= CSize-ShAmt)
265 if (ByteStart+ByteSize+ShAmt <= CSize)
266 return ExtractConstantBytes(CE->getOperand(0), ByteStart+ShAmt, ByteSize);
276 unsigned ShAmt = Amt->getZExtValue();
278 if ((ShAmt & 7) != 0)
280 ShAmt >>= 3;
283 if (ByteStart+ByteSize <= ShAmt)
[all...] |
| /external/llvm/lib/Support/ |
| APInt.cpp | [all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ThumbDisassemblerCore.h | [all...] |
| ARMDisassemblerCore.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 757 int ShAmt = (4-ByteSize)*8;
758 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
[all...] |
