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  /frameworks/base/core/java/android/util/
LruCache.java 352 int accesses = hitCount + missCount; local
353 int hitPercent = accesses != 0 ? (100 * hitCount / accesses) : 0;
  /frameworks/support/v4/java/android/support/v4/util/
LruCache.java 318 int accesses = hitCount + missCount; local
319 int hitPercent = accesses != 0 ? (100 * hitCount / accesses) : 0;
  /external/webkit/LayoutTests/fast/dom/Geolocation/script-tests/
clear-watch-invalid-id-crash.js 1 description("Tests for a crash when clearWatch() is called with a zero ID.<br><br>We call clearWatch() with a request in progress then navigate the page. This accesses the watchers map during cleanup and triggers the crash. This page should not be visible when the test completes.");
  /external/v8/test/mjsunit/compiler/
variables.js 69 // Parameters rewritten to property accesses. Using the name 'arguments'
71 // rewritten to explicit property accesses.
  /external/oprofile/events/mips/24K/
events 24 event:0x5 counters:0 um:zero minimum:500 name:ITLB_ACCESSES : 5-0 Instruction micro-TLB accesses
25 event:0x6 counters:0 um:zero minimum:500 name:DTLB_ACCESSES : 6-0 Data micro-TLB accesses
26 event:0x7 counters:0 um:zero minimum:500 name:JTLB_INSN_ACCESSES : 7-0 Joint TLB instruction accesses
27 event:0x8 counters:0 um:zero minimum:500 name:JTLB_DATA_ACCESSES : 8-0 Joint TLB data (non-instruction) accesses
28 event:0x9 counters:0 um:zero minimum:500 name:ICACHE_ACCESSES : 9-0 Instruction cache accesses
29 event:0xa counters:0 um:zero minimum:500 name:DCACHE_ACCESSES : 10-0 Data cache accesses
40 event:0x16 counters:0 um:zero minimum:500 name:L2_CACHE_MISSES : 22-0 L2 cache accesses that missed in the cache
103 event:0x415 counters:1 um:zero minimum:500 name:L2_CACHE_ACCESSES : 21-1 Accesses to the L2 cache
  /external/oprofile/events/mips/34K/
events 24 event:0x5 counters:0 um:zero minimum:500 name:ITLB_ACCESSES : 5-0 Instruction micro-TLB accesses
25 event:0x6 counters:0 um:zero minimum:500 name:DTLB_ACCESSES : 6-0 Data micro-TLB accesses
26 event:0x7 counters:0 um:zero minimum:500 name:JTLB_INSN_ACCESSES : 7-0 Joint TLB instruction accesses
27 event:0x8 counters:0 um:zero minimum:500 name:JTLB_DATA_ACCESSES : 8-0 Joint TLB data (non-instruction) accesses
28 event:0x9 counters:0 um:zero minimum:500 name:ICACHE_ACCESSES : 9-0 Instruction cache accesses
29 event:0xa counters:0 um:zero minimum:500 name:DCACHE_ACCESSES : 10-0 Data cache accesses
40 event:0x16 counters:0 um:zero minimum:500 name:L2_CACHE_MISSES : 22-0 L2 cache accesses that missed in the cache
111 event:0x415 counters:1 um:zero minimum:500 name:L2_CACHE_ACCESSES : 21-1 Accesses to the L2 cache
  /external/oprofile/events/i386/atom/
events 16 event:0x08 counters:0,1 um:data_tlb_misses minimum:6000 name:DATA_TLB_MISSES : Memory accesses that missed the DTLB
32 event:0x2B counters:0,1 um:core,mesi minimum:6000 name:L2_LOCK : L2 locked accesses
38 event:0x40 counters:0,1 um:l1d_cache minimum:6000 name:L1D_CACHE : L1d Cache accesses
62 event:0x80 counters:0,1 um:icache minimum:6000 name:ICACHE : Instruction cache accesses
unit_masks 14 0x07 dtlb_miss Memory accesses that missed the DTLB
43 0x03 accesses Instruction fetches
  /external/oprofile/events/mips/1004K/
events 24 event:0x5 counters:0 um:zero minimum:500 name:ITLB_ACCESSES : 5-0 Instruction micro-TLB accesses
25 event:0x6 counters:0 um:zero minimum:500 name:DTLB_ACCESSES : 6-0 Data micro-TLB accesses
26 event:0x7 counters:0 um:zero minimum:500 name:JTLB_INSN_ACCESSES : 7-0 Joint TLB instruction accesses
27 event:0x8 counters:0 um:zero minimum:500 name:JTLB_DATA_ACCESSES : 8-0 Joint TLB data (non-instruction) accesses
28 event:0x9 counters:0 um:zero minimum:500 name:ICACHE_ACCESSES : 9-0 Instruction cache accesses
29 event:0xa counters:0 um:zero minimum:500 name:DCACHE_ACCESSES : 10-0 Data cache accesses
40 event:0x16 counters:0 um:zero minimum:500 name:L2_CACHE_MISSES : 22-0 L2 cache accesses that missed in the cache
119 event:0x415 counters:1 um:zero minimum:500 name:L2_CACHE_ACCESSES : 21-1 Accesses to the L2 cache
  /external/webkit/LayoutTests/dom/html/level2/html/
HTMLScriptElement06.js 78 htmlFor is described as for future use. Test accesses the value, but makes no assertions about its value.
HTMLScriptElement07.js 78 event is described as for future use. Test accesses the value, but makes no assertions about its value.
  /external/webkit/LayoutTests/dom/xhtml/level2/html/
HTMLScriptElement06.js 78 htmlFor is described as for future use. Test accesses the value, but makes no assertions about its value.
HTMLScriptElement07.js 78 event is described as for future use. Test accesses the value, but makes no assertions about its value.
  /external/oprofile/events/mips/74K/
events 22 event:0x4 counters:0,2 um:zero minimum:500 name:ITLB_ACCESSES : 4-0 Instruction micro-TLB accesses
24 event:0x6 counters:0,2 um:zero minimum:500 name:ICACHE_ACCESSES : 6-0 Instruction cache accesses including speculative instructions
41 event:0x17 counters:0,2 um:zero minimum:500 name:DCACHE_LOAD_ACCESSES : 23-0 Counts all accesses to the data cache caused by load instructions
43 event:0x19 counters:0,2 um:zero minimum:500 name:JTLB_DATA_ACCESSES : 25-0 Joint TLB data (non-instruction) accesses
117 event:0x417 counters:1,3 um:zero minimum:500 name:DCACHE_ACCESSES : 23-1 Data cache accesses
122 event:0x41c counters:1,3 um:zero minimum:500 name:L2_CACHE_ACCESSES : 28-1 Accesses to the L2 cache
  /external/oprofile/events/i386/nehalem/
events 55 event:0x4F counters:0,1,2,3 um:ept minimum:6000 name:EPT : Counts Extended Page Directory Entry accesses. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.
62 event:0x80 counters:0,1,2,3 um:l1i minimum:6000 name:L1I : Counts L1i instruction cache accesses.
64 event:0x82 counters:0,1,2,3 um:large_itlb minimum:6000 name:LARGE_ITLB : Counts number of large ITLB accesses
81 event:0xBA counters:0,1,2,3 um:pic_accesses minimum:6000 name:PIC_ACCESSES : Counts number of TPR accesses
  /external/oprofile/events/x86-64/family11h/
events 38 event:0x40 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_ACCESSES : Data cache accesses
46 event:0x47 counters:0,1,2,3 um:zero minimum:500 name:MISALIGNED_ACCESSES : Misaligned Accesses
115 event:0xe0 counters:0,1,2,3 um:dramaccess minimum:500 name:DRAM_ACCESSES : DRAM accesses
  /external/oprofile/events/x86-64/hammer/
events 38 event:0x40 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_ACCESSES : Data cache accesses
46 event:0x47 counters:0,1,2,3 um:zero minimum:500 name:MISALIGNED_ACCESSES : Misaligned Accesses
110 event:0xe0 counters:0,1,2,3 um:page_access minimum:500 name:DRAM_ACCESSES : DRAM accesses
  /external/libvpx/vp8/common/ppc/
loopfilter_filters_altivec.asm 1174 ;# 16 unaligned word accesses
    [all...]
  /external/dropbear/libtomcrypt/
crypt.tex     [all...]
  /external/v8/test/mjsunit/
unicode-test.js     [all...]

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