| /external/llvm/lib/CodeGen/ |
| AllocationOrder.cpp | 29 const TargetRegisterClass *RC = VRM.getRegInfo().getRegClass(VirtReg);
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| CalcSpillWeights.cpp | 79 const TargetRegisterClass *rc = mri.getRegClass(reg);
193 const TargetRegisterClass *OldRC = MRI.getRegClass(reg);
210 TII->getRegClass(I->getDesc(), I.getOperandNo(), TRI);
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| Spiller.cpp | 88 const TargetRegisterClass *trc = mri->getRegClass(li->reg);
222 const TargetRegisterClass *RC = mf->getRegInfo().getRegClass(LRE.getReg());
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| RegisterCoalescer.cpp | 149 Dst = tri_.getMatchingSuperReg(Dst, SrcSub, MRI.getRegClass(Src));
152 } else if (!MRI.getRegClass(Src)->contains(Dst)) {
165 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
166 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
182 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
183 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
593 !mri_->constrainRegClass(IntB.reg, mri_->getRegClass(IntA.reg)))
705 const TargetRegisterClass *RC = tii_->getRegClass(MCID, 0, tri_);
707 if (mri_->getRegClass(DstReg) != RC)
719 const TargetRegisterClass *DstRC = mri_->getRegClass(DstReg)
[all...] |
| MachineLICM.cpp | 628 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
664 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
678 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
882 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
[all...] |
| MachineSink.cpp | 121 const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg);
122 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg);
450 if (!TII->isSafeToMoveRegClassDefs(MRI->getRegClass(Reg)))
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| PeepholeOptimizer.cpp | 235 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);
320 if (MRI->getRegClass(SrcSrc) != MRI->getRegClass(Def))
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| VirtRegMap.cpp | 132 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
355 << MRI.getRegClass(Reg)->getName() << "\n";
363 << "] " << MRI.getRegClass(Reg)->getName() << "\n";
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| InlineSpiller.cpp | 528 MRI.getRegClass(SVI.SpillReg), &TRI);
852 MRI.getRegClass(NewLI.reg), &TRI);
868 MRI.getRegClass(NewLI.reg), &TRI);
[all...] |
| RegAllocBasic.cpp | 319 << MRI->getRegClass(VirtReg->reg)->getName()
340 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front());
486 RegClassInfo.getOrder(MRI->getRegClass(VirtReg.reg));
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| TwoAddressInstructionPass.cpp | [all...] |
| TargetInstrInfoImpl.cpp | 210 const TargetRegisterClass *RC = MRI.getRegClass(FoldReg);
215 if (RC->hasSubClassEq(MRI.getRegClass(LiveReg)))
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| MachineRegisterInfo.cpp | 52 const TargetRegisterClass *OldRC = getRegClass(Reg);
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| UnreachableBlockElim.cpp | 201 MRI.constrainRegClass(Input, MRI.getRegClass(Output));
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| VirtRegRewriter.cpp | 445 const TargetRegisterClass* RC = MF.getRegInfo().getRegClass(VirtReg);
[all...] |
| RegAllocLinearScan.cpp | 490 const TargetRegisterClass *RC = mri_->getRegClass(cur.reg);
[all...] |
| CriticalAntiDepBreaker.cpp | 210 NewRC = TII->getRegClass(MI->getDesc(), i, TRI);
298 NewRC = TII->getRegClass(MI->getDesc(), i, TRI);
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 112 RC = TII->getRegClass(II, i+II.getNumDefs(), TRI);
135 DstRC = MRI->getRegClass(VRBase);
192 const TargetRegisterClass *RC = TII->getRegClass(II, i, TRI);
210 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
285 const TargetRegisterClass *SrcRC = MRI->getRegClass(VReg);
288 DstRC = TII->getRegClass(*II, IIOpNum, TRI);
446 const TargetRegisterClass *TRC = MRI->getRegClass(SrcReg);
451 const TargetRegisterClass *TRC = MRI->getRegClass(VReg);
459 if (VRBase == 0 || SRC != MRI->getRegClass(VRBase)) {
484 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg)
[all...] |
| /external/llvm/lib/Target/Blackfin/ |
| BlackfinISelDAGToDAG.cpp | 157 TII.getRegClass(DefMCID, UI.getUse().getResNo(), TRI);
163 TII.getRegClass(UseMCID, UseMCID.getNumDefs()+UI.getOperandNo(), TRI);
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| /external/llvm/lib/Target/ |
| TargetInstrInfo.cpp | 31 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
45 return TRI->getRegClass(RegClass);
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| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.h | 192 CodeGenRegisterClass *getRegClass(Record*);
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| CodeGenTarget.h | 115 return *getRegBank().getRegClass(R);
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| /external/llvm/include/llvm/CodeGen/ |
| MachineRegisterInfo.h | 187 /// getRegClass - Return the register class of the specified virtual register.
189 const TargetRegisterClass *getRegClass(unsigned Reg) const {
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| /external/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | 55 /// getRegClass - Givem a machine instruction descriptor, returns the register
57 const TargetRegisterClass *getRegClass(const MCInstrDesc &TID,
[all...] |
| TargetRegisterInfo.h | 494 /// getRegClass - Returns the register class associated with the enumeration
496 const TargetRegisterClass *getRegClass(unsigned i) const {
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