| /external/llvm/lib/CodeGen/ |
| AllocationOrder.cpp | 29 const TargetRegisterClass *RC = VRM.getRegInfo().getRegClass(VirtReg);
31 VRM.getRegInfo().getRegAllocationHint(VirtReg);
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| PHIEliminationUtils.cpp | 36 MachineRegisterInfo& MRI = MBB->getParent()->getRegInfo();
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| VirtRegMap.cpp | 56 MRI = &mf.getRegInfo();
79 ImplicitDefed.resize(MF->getRegInfo().getNumVirtRegs());
93 unsigned NumRegs = MF->getRegInfo().getNumVirtRegs();
132 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
347 const MachineRegisterInfo &MRI = MF->getRegInfo();
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| PHIElimination.cpp | 108 MRI = &MF.getRegInfo();
224 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
225 entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
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| CalcSpillWeights.cpp | 90 MachineRegisterInfo &mri = MF.getRegInfo();
190 MachineRegisterInfo &MRI = MF.getRegInfo();
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| Spiller.cpp | 68 mri = &mf.getRegInfo();
222 const TargetRegisterClass *RC = mf->getRegInfo().getRegClass(LRE.getReg());
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| DeadMachineInstructionElim.cpp | 87 MRI = &MF.getRegInfo();
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| OptimizePHIs.cpp | 65 MRI = &Fn.getRegInfo();
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| LiveRangeEdit.cpp | 35 MachineRegisterInfo &MRI = VRM.getRegInfo();
217 MachineRegisterInfo &MRI = VRM.getRegInfo();
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| MachineInstr.cpp | 109 AddRegOperandToRegInfo(&MF->getRegInfo());
173 AddRegOperandToRegInfo(&MF->getRegInfo());
575 /// getRegInfo - If this instruction is embedded into a MachineFunction,
578 MachineRegisterInfo *MachineInstr::getRegInfo() {
580 return &MBB->getParent()->getRegInfo();
614 MachineRegisterInfo *RegInfo = getRegInfo();
726 MachineRegisterInfo *RegInfo = getRegInfo();
[all...] |
| TargetInstrInfoImpl.cpp | 209 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
322 const MachineRegisterInfo &MRI = MF.getRegInfo();
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| LocalStackSlotAllocation.cpp | 322 BaseReg = Fn.getRegInfo().createVirtualRegister(RC);
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| /dalvik/vm/compiler/codegen/ |
| RallocUtil.cpp | 83 static RegisterInfo *getRegInfo(CompilationUnit *cUnit, int reg)
107 RegisterInfo *info1 = getRegInfo(cUnit, reg1);
108 RegisterInfo *info2 = getRegInfo(cUnit, reg2);
126 RegisterInfo *info = getRegInfo(cUnit, reg);
439 RegisterInfo *p = getRegInfo(cUnit, reg);
469 RegisterInfo *p = getRegInfo(cUnit, rl.lowReg);
485 RegisterInfo *p = getRegInfo(cUnit, rl.lowReg);
496 RegisterInfo *infoLo = getRegInfo(cUnit, rl.lowReg);
497 RegisterInfo *infoHi = getRegInfo(cUnit, rl.highReg);
527 RegisterInfo *p = getRegInfo(cUnit, rl.lowReg)
[all...] |
| /external/llvm/lib/Target/PTX/ |
| PTXMFInfoExtract.cpp | 53 MachineRegisterInfo &MRI = MF.getRegInfo();
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| PTXISelLowering.cpp | 274 unsigned Reg = MF.getRegInfo().createVirtualRegister(TRC);
275 MF.getRegInfo().addLiveIn(VA.getLocReg(), Reg);
330 DAG.getMachineFunction().getRegInfo().addLiveOut(Reg);
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| /external/llvm/lib/Target/ARM/ |
| ARMFrameLowering.cpp | 363 assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) &&
562 MF.getRegInfo().isLiveIn(Reg))
[all...] |
| Thumb1FrameLowering.cpp | 239 assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) &&
309 MF.getRegInfo().isLiveIn(Reg))
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| /external/llvm/lib/Target/Alpha/ |
| AlphaISelLowering.cpp | 42 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
43 MF.getRegInfo().addLiveIn(PReg, VReg);
497 if (DAG.getMachineFunction().getRegInfo().liveout_empty())
498 DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg);
514 if (std::find(DAG.getMachineFunction().getRegInfo().liveout_begin(),
515 DAG.getMachineFunction().getRegInfo().liveout_end(), ArgReg1)
516 == DAG.getMachineFunction().getRegInfo().liveout_end())
517 DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg1);
520 if (std::find(DAG.getMachineFunction().getRegInfo().liveout_begin(),
521 DAG.getMachineFunction().getRegInfo().liveout_end(), ArgReg2
[all...] |
| AlphaInstrInfo.cpp | 348 MachineRegisterInfo &RegInfo = MF->getRegInfo();
373 MachineRegisterInfo &RegInfo = MF->getRegInfo();
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| /external/llvm/lib/Target/CellSPU/ |
| SPUFrameLowering.cpp | 258 MF.getRegInfo().setPhysRegUnused(SPU::R0);
259 MF.getRegInfo().setPhysRegUnused(SPU::R1);
260 MF.getRegInfo().setPhysRegUnused(SPU::R2);
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| /external/llvm/lib/Target/SystemZ/ |
| SystemZFrameLowering.cpp | 123 assert(MF.getRegInfo().isPhysRegUsed(SystemZ::R15D) &&
179 assert(MF.getRegInfo().isPhysRegUsed(SystemZ::R15D) &&
359 MachineRegisterInfo &MRI = MF.getRegInfo();
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| /external/llvm/include/llvm/CodeGen/ |
| MachineFunction.h | 152 /// getRegInfo - Return information about the registers currently in use.
154 MachineRegisterInfo &getRegInfo() { return *RegInfo; }
155 const MachineRegisterInfo &getRegInfo() const { return *RegInfo; }
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| /external/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 104 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
110 I = MF->getRegInfo().livein_begin(),
111 E = MF->getRegInfo().livein_end(); I != E; ++I) {
117 I = MF->getRegInfo().liveout_begin(),
118 E = MF->getRegInfo().liveout_end(); I != E; ++I) {
730 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR);
731 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired();
743 MF.getRegInfo().setPhysRegUnused(LR);
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 101 if (MF.getRegInfo().liveout_empty()) {
104 MF.getRegInfo().addLiveOut(RVLocs[i].getLocReg());
131 if (MF.getRegInfo().liveout_empty())
132 MF.getRegInfo().addLiveOut(SP::I0);
158 MachineRegisterInfo &RegInfo = MF.getRegInfo();
187 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi);
213 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg);
296 Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass);
325 MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreFrameLowering.cpp | 343 bool LRUsed = MF.getRegInfo().isPhysRegUsed(XCore::LR);
347 MF.getRegInfo().setPhysRegUnused(XCore::LR);
|
