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  /external/v8/test/mjsunit/regress/
regress-815.js 29 // end up in a spilled scope in code that only worked in a register
32 // The code generated for unary + assumes that we are not in a spilled
38 // in a spilled scope:
regress-r4998.js 71 // MakeMergeable has forced the loop variable x7 to be spilled,
  /external/llvm/lib/CodeGen/
ShrinkWrapping.cpp 540 // Machine CFG around which CSRs must be spilled and restored.
546 /// addUsesForMEMERegion - add uses of CSRs spilled or restored in
670 /// calcSpillPlacements - determine which CSRs should be spilled
672 /// of changes to spilled reg sets. Add MBB to the set of blocks
712 // Reset all regs spilled in MBB that are also spilled in EntryBlock.
833 // Add uses for CSRs spilled or restored at branch, join points.
948 CSRegSet spilled = BI->second; local
1002 CSRegSet spilled; local
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RegAllocPBQP.cpp 145 /// spilled. Used to support stack slot coloring.
146 void addStackInterval(const LiveInterval *spilled,MachineRegisterInfo* mri);
491 void RegAllocPBQP::addStackInterval(const LiveInterval *spilled,
493 int stackSlot = vrm->getStackSlot(spilled->reg);
499 const TargetRegisterClass *RC = mri->getRegClass(spilled->reg);
510 LiveInterval &rhsInterval = lis->getInterval(spilled->reg);
547 DEBUG(dbgs() << "VREG " << vreg << " -> SPILLED (Cost: "
614 // Filter out zero regs - they're for intervals that were spilled.
RegAllocLinearScan.cpp 1292 SmallSet<unsigned, 8> spilled; local
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  /external/grub/docs/
texinfo.tex     [all...]
  /ndk/sources/host-tools/sed-4.2.1/build-aux/
texinfo.tex     [all...]

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