| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 75 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
148 // Create the reg, emit the copy.
173 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
174 if (TargetRegisterInfo::isVirtualRegister(Reg))
175 return Reg;
188 // If the specific node value is only used by a CopyToReg and the dest reg
208 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
209 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
210 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
212 VRBase = Reg;
[all...] |
| /external/llvm/lib/CodeGen/ |
| VirtRegMap.cpp | 233 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
234 if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG)
235 Used.set(Virt2PhysMap[Reg]);
240 for (unsigned Reg = 1; Reg < NumRegs; ++Reg) {
241 if (Allocatable[Reg] && !Used[Reg] && !LIs->hasInterval(Reg)) {
243 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
[all...] |
| CriticalAntiDepBreaker.cpp | 64 unsigned Reg = *I;
65 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
66 KillIndices[Reg] = BB->size();
67 DefIndices[Reg] = ~0u;
70 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
86 unsigned Reg = *I;
87 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
88 KillIndices[Reg] = BB->size();
89 DefIndices[Reg] = ~0u;
92 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias)
[all...] |
| MachineSink.cpp | 90 bool AllUsesDominatedByBlock(unsigned Reg, MachineBasicBlock *MBB,
142 MachineSinking::AllUsesDominatedByBlock(unsigned Reg,
147 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
150 if (MRI->use_nodbg_empty(Reg))
175 I = MRI->use_nodbg_begin(Reg), E = MRI->use_nodbg_end();
189 I = MRI->use_nodbg_begin(Reg), E = MRI->use_nodbg_end();
303 unsigned Reg = MO.getReg();
304 if (Reg == 0 || !TargetRegisterInfo::isPhysicalRegister(Reg))
306 if (MRI->hasOneNonDBGUse(Reg))
[all...] |
| PHIElimination.cpp | 196 assert(MPhi->getOperand(0).getSubReg() == 0 && "Can't handle sub-reg PHIs");
413 unsigned Reg = BBI->getOperand(i).getReg();
421 !LV.isLiveIn(Reg, MBB) && LV.isLiveOut(Reg, *PreMBB)) {
|
| PeepholeOptimizer.cpp | 280 unsigned Reg = MO.getReg();
281 if (!Reg)
284 Def = Reg;
289 Src = Reg;
308 unsigned Reg = MO.getReg();
309 if (!Reg)
312 SrcDef = Reg;
317 SrcSrc = Reg;
361 unsigned Reg = MI->getOperand(0).getReg();
362 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
[all...] |
| PostRASchedulerList.cpp | 371 unsigned Reg = *I;
372 KillIndices[Reg] = BB->size();
374 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
386 unsigned Reg = *I;
387 KillIndices[Reg] = BB->size();
389 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
459 unsigned Reg = MO.getReg();
460 if (Reg == 0) continue;
465 KillIndices[Reg] = ~0u;
468 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
[all...] |
| PrologEpilogInserter.cpp | 223 unsigned Reg = CSRegs[i];
224 if (Fn.getRegInfo().isPhysRegUsed(Reg)) {
225 // If the reg is modified, save it!
226 CSI.push_back(CalleeSavedInfo(Reg));
228 for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
231 CSI.push_back(CalleeSavedInfo(Reg));
249 unsigned Reg = I->getReg();
250 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg);
253 if (RegInfo->hasReservedSpillSlot(Fn, Reg, FrameIdx)) {
262 FixedSlot->Reg != Reg
[all...] |
| TargetInstrInfoImpl.cpp | 356 unsigned Reg = MO.getReg();
357 if (Reg == 0)
361 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
366 if (!MRI.def_empty(Reg))
369 if (AllocatableRegs.test(Reg))
372 for (const unsigned *Alias = TRI.getAliasSet(Reg); *Alias; ++Alias) {
|
| VirtRegRewriter.cpp | 68 static void substitutePhysReg(MachineOperand &MO, unsigned Reg,
71 MO.substPhysReg(Reg, TRI);
75 // We assume that partial defs have already been decorated with a super-reg
80 MI.addRegisterKilled(Reg, &TRI, /*AddIfNotFound=*/ true);
82 MO.setReg(Reg);
111 unsigned reg = li->reg; local
113 if (TargetRegisterInfo::isPhysicalRegister(reg)) {
115 mri->setPhysRegUsed(reg);
118 if (!VRM.hasPhys(reg))
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb1FrameLowering.cpp | 85 unsigned Reg = CSI[i].getReg();
87 switch (Reg) {
93 if (Reg == FramePtr)
102 if (Reg == FramePtr)
173 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
175 if (Reg == CSRegs[i])
300 unsigned Reg = CSI[i-1].getReg();
306 if (Reg == ARM::LR) {
309 MF.getRegInfo().isLiveIn(Reg))
314 MBB.addLiveIn(Reg);
[all...] |
| Thumb2ITBlockPass.cpp | 66 unsigned Reg = MO.getReg();
67 if (!Reg || Reg == ARM::ITSTATE || Reg == ARM::SP)
70 LocalUses.push_back(Reg);
72 LocalDefs.push_back(Reg);
76 unsigned Reg = LocalUses[i];
77 Uses.insert(Reg);
78 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
84 unsigned Reg = LocalDefs[i]
[all...] |
| MLxExpansionPass.cpp | 63 bool hasRAWHazard(unsigned Reg, MachineInstr *MI) const;
87 unsigned Reg = MI->getOperand(1).getReg();
88 if (TargetRegisterInfo::isPhysicalRegister(Reg))
92 MachineInstr *DefMI = MRI->getVRegDef(Reg);
97 Reg = DefMI->getOperand(1).getReg();
98 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
99 DefMI = MRI->getVRegDef(Reg);
103 Reg = DefMI->getOperand(2).getReg();
104 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
105 DefMI = MRI->getVRegDef(Reg);
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeAsmPrinter.cpp | 138 unsigned Reg = CSI[i].getReg();
139 unsigned RegNum = MBlazeRegisterInfo::getRegisterNumbering(Reg);
140 if (MBlaze::GPRRegisterClass->contains(Reg))
|
| /external/llvm/lib/Target/Mips/ |
| MipsFrameLowering.cpp | 215 unsigned Reg = I->getReg();
217 // If Reg is a double precision register, emit two cfa_offsets,
219 if (Mips::AFGR64RegisterClass->contains(Reg)) {
220 const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
233 // Reg is either in CPURegs or FGR32.
235 SrcML = MachineLocation(Reg);
|
| MipsAsmPrinter.cpp | 115 unsigned Reg = CSI[i].getReg();
116 if (Mips::CPURegsRegisterClass->contains(Reg))
119 unsigned RegNum = MipsRegisterInfo::getRegisterNumbering(Reg);
120 if (Mips::AFGR64RegisterClass->contains(Reg)) {
133 unsigned Reg = CSI[i].getReg();
134 unsigned RegNum = MipsRegisterInfo::getRegisterNumbering(Reg);
367 // Load/Store memory operands -- imm($reg)
|
| /external/llvm/lib/Target/Sparc/ |
| DelaySlotFiller.cpp | 38 /// Target machine description which we query for reg. names, data
72 unsigned Reg);
216 unsigned Reg = MO.getReg();
219 //check whether Reg is defined or used before delay slot.
220 if (IsRegInSet(RegDefs, Reg) || IsRegInSet(RegUses, Reg))
224 //check whether Reg is defined before delay slot.
225 if (IsRegInSet(RegDefs, Reg))
243 const MachineOperand &Reg = MI->getOperand(0);
244 assert(Reg.isReg() && "JMPL first operand is not a register.")
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZFrameLowering.cpp | 243 unsigned Reg = CSI[i].getReg();
244 if (!SystemZ::FP64RegClass.contains(Reg)) {
245 unsigned Offset = RegSpillOffsets[Reg];
248 LowReg = Reg; StartOffset = Offset;
251 HighReg = Reg; EndOffset = RegSpillOffsets[Reg];
278 unsigned Reg = CSI[i].getReg();
280 MBB.addLiveIn(Reg);
281 if (Reg != LowReg && Reg != HighReg
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86CodeEmitter.cpp | 169 unsigned Reg = MO.getReg();
170 if (X86InstrInfo::isX86_64NonExtLowByteReg(Reg))
521 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
528 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
536 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
707 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 219 unsigned Reg = MI.getOperand(0).getReg();
222 assert(XCore::GRRegsRegisterClass->contains(Reg) &&
239 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
245 .addReg(Reg, getKillRegState(isKill))
250 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
260 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
266 .addReg(Reg, getKillRegState(isKill))
271 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
289 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
295 .addReg(Reg, getKillRegState(isKill)
[all...] |
| /external/llvm/lib/ExecutionEngine/JIT/ |
| JITDwarfEmitter.cpp | 120 unsigned Reg = RI->getDwarfRegNum(Src.getReg(), true);
125 JCE->emitULEB128Bytes(Reg);
127 } else if (Reg < 64) {
128 JCE->emitByte(dwarf::DW_CFA_offset + Reg);
132 JCE->emitULEB128Bytes(Reg);
|
| /external/llvm/lib/MC/MCParser/ |
| COFFAsmParser.cpp | 252 unsigned Reg;
253 if (ParseSEHRegisterNumber(Reg))
260 getStreamer().EmitWin64EHPushReg(Reg);
265 unsigned Reg;
267 if (ParseSEHRegisterNumber(Reg))
284 getStreamer().EmitWin64EHSetFrame(Reg, Off);
306 unsigned Reg;
308 if (ParseSEHRegisterNumber(Reg))
326 getStreamer().EmitWin64EHSaveReg(Reg, Off);
333 unsigned Reg;
[all...] |
| /external/llvm/lib/Target/Blackfin/ |
| BlackfinISelLowering.cpp | 189 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
190 MF.getRegInfo().addLiveIn(VA.getLocReg(), Reg);
191 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
348 // Build a sequence of copy-to-reg nodes chained together with token
389 unsigned Reg = RV.getLocReg();
391 Chain = DAG.getCopyFromReg(Chain, dl, Reg,
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelDAGToDAG.cpp | 42 SDValue Reg;
65 if (BaseType == RegBase && Base.Reg.getNode() != 0) {
66 errs() << "Base.Reg ";
67 Base.Reg.getNode()->dump();
173 if (AM.BaseType != MSP430ISelAddressMode::RegBase || AM.Base.Reg.getNode()) {
180 AM.Base.Reg = N;
202 && AM.Base.Reg.getNode() == 0) {
257 if (!AM.Base.Reg.getNode())
258 AM.Base.Reg = CurDAG->getRegister(0, VT);
263 AM.Base.Reg;
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 320 llvm_unreachable("Impossible reg-to-reg copy");
389 // FIXME: We need a scatch reg here. The trouble with using R0 is that
422 unsigned Reg = 0;
425 Reg = PPC::CR0;
428 Reg = PPC::CR1;
431 Reg = PPC::CR2;
434 Reg = PPC::CR3;
437 Reg = PPC::CR4;
440 Reg = PPC::CR5
[all...] |
