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  /dalvik/vm/mterp/x86-atom/
binopF.S 20 * specify an instruction that performs "%xmm0 = %xmm0 op %xmm1"
34 FFETCH_ADV 2, %eax # %eax<- next instruction hi; fetch, advance
39 FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
binopLit8.S 20 * to specify an instruction that performs "%ecx = %ecx op %edx"
36 FFETCH_ADV 2, %eax # %eax<- next instruction hi; fetch, advance
40 FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
binopLit8S.S 20 * to specify an instruction that performs "%edx = %edx op %cl"
36 FFETCH_ADV 2, %eax # %eax<- next instruction hi; fetch, advance
40 FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
binopS.S 20 * specify an instruction that performs "%edx = %edx op %cl"
34 FFETCH_ADV 2, %eax # %eax<- next instruction hi; fetch, advance
39 FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
OP_CMPL_FLOAT.S 41 FFETCH_ADV 2, %eax # %eax<- next instruction hi; fetch, advance
50 FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
55 FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
59 FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
63 FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
OP_EXECUTE_INLINE_RANGE.S 19 * Code: Executes a "native inline" instruction. Uses no substitutions.
23 * Description: Executes a "native inline" instruction. This instruction
72 FFETCH_ADV 3, %eax # %eax<- next instruction hi; fetch, advance
75 FGETOP_JMP 3, %eax # jump to next instruction; getop, jmp
  /external/llvm/include/llvm/Target/
TargetOpcodes.h 10 // This file defines the target independent instruction opcodes.
19 /// Invariant opcodes: All instruction sets have these as their low opcodes.
21 /// Every instruction defined here must also appear in Target.td and the order
32 /// KILL - This instruction is a noop that is used only to adjust the
37 /// EXTRACT_SUBREG - This instruction takes two operands: a register
43 /// INSERT_SUBREG - This instruction takes three operands: a register that
54 /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that
56 /// often zero, because it is commonly used to assert that the instruction
60 /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain
62 /// used between instruction selection and MachineInstr creation, befor
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  /external/llvm/lib/Target/PowerPC/
PPCInstrInfo.h 1 //===- PPCInstrInfo.h - PowerPC Instruction Information ---------*- C++ -*-===//
27 /// per-instruction flags. These must match the corresponding definitions in
31 // PPC970 Instruction Flags. These flags describe the characteristics of the
35 /// PPC970_First - This instruction starts a new dispatch group, so it will
39 /// PPC970_Single - This instruction starts a new dispatch group and
40 /// terminates it, so it will be the sole instruction in the group.
43 /// PPC970_Cracked - This instruction is cracked into two pieces, requiring
48 /// an instruction is issued to.
53 /// These are the various PPC970 execution unit pipelines. Each instruction
55 PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction
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PPCRelocations.h 39 // reloc_absolute_high - Absolute relocation, for the loadhi instruction
41 // address into the low 16-bits of the instruction.
44 // reloc_absolute_low - Absolute relocation, for the la instruction (which
46 // address into the low 16-bits of the instruction.
50 // instruction which have two implicit zero bits.
  /external/llvm/lib/Transforms/Scalar/
DCE.cpp 22 #include "llvm/Instruction.h"
43 Instruction *Inst = DI++;
61 "Dead Instruction Elimination", false, false)
91 std::vector<Instruction*> WorkList;
101 Instruction *I = WorkList.back();
104 if (isInstructionTriviallyDead(I)) { // If the instruction is dead.
105 // Loop over all of the values that the instruction uses, if there are
110 if (Instruction *Used = dyn_cast<Instruction>(*OI))
113 // Remove the instruction
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CorrelatedValuePropagation.cpp 38 bool processMemAccess(Instruction *I);
118 bool CorrelatedValuePropagation::processMemAccess(Instruction *I) {
142 if (isa<Instruction>(Op0) &&
143 cast<Instruction>(Op0)->getParent() == C->getParent())
184 Instruction *II = BI++;
186 case Instruction::Select:
189 case Instruction::PHI:
192 case Instruction::ICmp:
193 case Instruction::FCmp:
196 case Instruction::Load
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  /external/webkit/Source/JavaScriptCore/interpreter/
Interpreter.h 54 struct Instruction;
127 NEVER_INLINE bool resolve(CallFrame*, Instruction*, JSValue& exceptionValue);
128 NEVER_INLINE bool resolveSkip(CallFrame*, Instruction*, JSValue& exceptionValue);
129 NEVER_INLINE bool resolveGlobal(CallFrame*, Instruction*, JSValue& exceptionValue);
130 NEVER_INLINE bool resolveGlobalDynamic(CallFrame*, Instruction*, JSValue& exceptionValue);
131 NEVER_INLINE void resolveBase(CallFrame*, Instruction* vPC);
132 NEVER_INLINE bool resolveBaseAndProperty(CallFrame*, Instruction*, JSValue& exceptionValue);
133 NEVER_INLINE ScopeChainNode* createExceptionScope(CallFrame*, const Instruction* vPC);
135 void tryCacheGetByID(CallFrame*, CodeBlock*, Instruction*, JSValue baseValue, const Identifier& propertyName, const PropertySlot&);
136 void uncacheGetByID(CodeBlock*, Instruction* vPC)
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  /frameworks/compile/linkloader/utils/
flush_cpu_cache.h 23 // invalidate the instruction cache; however, the toolchain of Android
25 // call to invalidate the instruction cache.
28 // instruction as well.
  /dalvik/dexgen/src/com/android/dexgen/dex/code/
OutputFinisher.java 34 * Processor for instruction lists, which takes a "first cut" of
35 * instruction selection as a basis and produces a "final cut" in the
48 /** whether any instruction has position info */
51 /** whether any instruction has local variable info */
99 * instruction for local variable information.
101 * @param insn {@code non-null;} instruction to scrutinize
102 * @return {@code true} iff the instruction refers to any
155 * a single instruction.
158 * @param insn {@code non-null;} instruction to scrutinize
209 * Adds an instruction to the output
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  /dalvik/docs/
java-constraints.html 142 The index of instruction <code>n+1</code> must equal the index of
143 instruction <code>n</code> plus the length of instruction
145 instruction. Opcodes modified by a <code>wide</code> instruction must
164 The last instruction in <code>code</code> array must end at index
184 Opcodes modified by a <code>wide</code> instruction must not be
185 directly reachable via a jump or branch instruction.
203 All targets of a <code>tableswitch</code> instruction must be opcodes
205 Opcodes modified by a <code>wide</code> instruction must not b
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  /dalvik/dx/src/com/android/dx/dex/code/
OutputFinisher.java 37 * Processor for instruction lists, which takes a "first cut" of
38 * instruction selection as a basis and produces a "final cut" in the
54 /** whether any instruction has position info */
57 /** whether any instruction has local variable info */
107 * instruction for local variable information.
109 * @param insn {@code non-null;} instruction to scrutinize
110 * @return {@code true} iff the instruction refers to any
163 * a single instruction.
166 * @param insn {@code non-null;} instruction to scrutinize
217 * Adds an instruction to the output
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  /dalvik/vm/analysis/
VerifySubs.h 25 * 0-15 instruction length (or 0 if this address doesn't hold an opcode)
28 * BranchTarget: other instructions can branch to this instruction
29 * GcPoint: this instruction is a GC safe point
30 * Visited: verifier has examined this instruction at least once
64 /* extract the relative branch offset from a branch instruction */
  /external/llvm/include/llvm/Assembly/
AssemblyAnnotationWriter.h 24 class Instruction;
39 /// after the basic block label, but before the first instruction in the
52 /// before an instruction is emitted.
53 virtual void emitInstructionAnnot(const Instruction *I,
57 /// right of an instruction or global value.
  /external/llvm/include/llvm/MC/
MCInstrInfo.h 1 //===-- llvm/MC/MCInstrInfo.h - Target Instruction Info ---------*- C++ -*-===//
10 // This file describes the target machine instruction set.
24 /// MCInstrInfo - Interface to description of machine instruction set
40 /// get - Return the machine instruction descriptor that corresponds to the
41 /// specified instruction opcode.
  /external/proguard/src/proguard/classfile/visitor/
DotClassClassVisitor.java 27 import proguard.classfile.instruction.*;
28 import proguard.classfile.instruction.visitor.InstructionVisitor;
64 public void visitAnyInstruction(Clazz clazz, Method method, CodeAttribute codeAttribute, int offset, Instruction instruction) {}
71 // Could this instruction be a .class construct?
  /external/proguard/src/proguard/optimize/peephole/
PeepholeOptimizer.java 27 import proguard.classfile.instruction.visitor.InstructionVisitor;
32 * instruction visitor. The instruction visitor should be using the same
50 * @param instructionVisitor the instruction visitor that performs
67 * @param instructionVisitor the instruction visitor that performs
  /external/v8/src/
disasm.h 61 // Writes one disassembled instruction into 'buffer' (0-terminated).
62 // Returns the length of the disassembled machine instruction in bytes.
63 int InstructionDecode(v8::internal::Vector<char> buffer, byte* instruction);
65 // Returns -1 if instruction does not mark the beginning of a constant pool,
67 int ConstantPoolSizeAt(byte* instruction);
disassembler.h 41 // instruction could be decoded.
47 // Decode instruction at pc and print disassembled instruction into f.
48 // Returns the instruction length in bytes, or 1 if the instruction could
  /external/apache-xml/src/main/java/org/apache/xalan/templates/
ElemPI.java 31 * Implement xsl:processing-instruction.
33 * <!ELEMENT xsl:processing-instruction %char-template;>
34 * <!ATTLIST xsl:processing-instruction
47 * The xsl:processing-instruction element has a required name
48 * attribute that specifies the name of the processing instruction node.
115 * Create a processing instruction in the result tree.
116 * The content of the xsl:processing-instruction element is a
117 * template for the string-value of the processing instruction node.
134 // Ignore processing instruction if name is null
146 // Ignore processing instruction, if invali
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  /external/llvm/include/llvm/Analysis/
PHITransAddr.h 17 #include "llvm/Instruction.h"
42 SmallVector<Instruction*, 4> InstInputs;
45 // If the address is an instruction, the whole thing is considered an input.
46 if (Instruction *I = dyn_cast<Instruction>(Addr))
84 SmallVectorImpl<Instruction*> &NewInsts);
103 SmallVectorImpl<Instruction*> &NewInsts);
105 /// AddAsInput - If the specified value is an instruction, add it as an input.
107 // If V is an instruction, it is now an input.
108 if (Instruction *VI = dyn_cast<Instruction>(V)
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