| /dalvik/dexgen/src/com/android/dexgen/rop/code/ |
| InsnList.java | 48 * Sets the instruction at the given index.
51 * @param insn {@code non-null;} the instruction to set at {@code n}
58 * Gets the last instruction. This is just a convenient shorthand for
61 * @return {@code non-null;} the last instruction
68 * Visits each instruction in the list, in order.
106 * the registers in each instruction are offset by the given
|
| /dalvik/dx/src/com/android/dx/dex/code/ |
| TargetInsn.java | 23 * Instruction which has a single branch target.
81 * Gets the unique branch target of this instruction.
90 * Gets the target address of this instruction. This is only valid
91 * to call if the target instruction has been assigned an address,
102 * Gets the branch offset of this instruction. This is only valid to
103 * call if both this and the target instruction each has been assigned
|
| InsnFormat.java | 33 * Base class for all instruction format handlers. Instruction format
48 * dump, of the given instruction. The instruction must be of this
51 * @param insn {@code non-null;} the instruction
78 * Returns the string form of the arguments to the given instruction.
79 * The instruction must be of this instance's format. If the instruction
85 * @param insn {@code non-null;} the instruction
91 * Returns the associated comment for the given instruction, if any
[all...] |
| /dalvik/dx/src/com/android/dx/rop/code/ |
| InsnList.java | 48 * Sets the instruction at the given index.
51 * @param insn {@code non-null;} the instruction to set at {@code n}
58 * Gets the last instruction. This is just a convenient shorthand for
61 * @return {@code non-null;} the last instruction
68 * Visits each instruction in the list, in order.
106 * the registers in each instruction are offset by the given
|
| /dalvik/opcode-gen/ |
| README.txt | 16 Notes on updating the sets of defined opcodes and instruction formats
33 * Implement/update the instruction in assembly in vm/mterp/{arm*,x86*}/...
34 * Verify by enabling the assembly (e.g. ARM) handler for that instruction
37 * Implement/update the instruction in
51 If you want to add, delete, or change instruction formats:
57 * Update the instruction format list in libdex/InstrUtils.h.
|
| /external/dropbear/ |
| cli-authinteract.c | 70 unsigned char *instruction = NULL; local
83 instruction = buf_getstring(ses.payload, NULL);
105 if (strlen(instruction) > 0) {
106 cleantext(instruction);
107 fprintf(stderr, "%s", instruction);
109 m_free(instruction);
|
| /external/llvm/include/llvm/CodeGen/ |
| LiveVariables.h | 11 // instruction in the function, this pass calculates the set of registers that
12 // are immediately dead after the instruction (i.e., the instruction calculates
14 // the instruction, but are never used after the instruction (i.e., they are
57 /// information: the set of blocks in which the instruction is live
58 /// throughout, the set of blocks in which the instruction is actually used,
62 /// There is one killing instruction, and AliveBlocks is empty.
69 /// lives until the specified instruction. Note that there cannot ever be a
100 /// machine instruction. Returns true if there was a kil
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetAsmParser.h | 42 /// ParseInstruction - Parse one assembly instruction.
44 /// The parser is positioned following the instruction name. The target
45 /// specific instruction parser should parse the entire instruction and
50 /// \param Name - The instruction name.
71 /// instruction as an actual MCInst and emit it to the specified MCStreamer.
|
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.h | 1 //===- XCoreInstrInfo.h - XCore Instruction Information ---------*- C++ -*-===//
31 /// such, whenever a client has an instance of instruction info, it should
36 /// isLoadFromStackSlot - If the specified machine instruction is a direct
39 /// not, return 0. This predicate must return 0 if the instruction has
44 /// isStoreToStackSlot - If the specified machine instruction is a direct
47 /// not, return 0. This predicate must return 0 if the instruction has
|
| /external/llvm/lib/Transforms/InstCombine/ |
| InstructionCombining.cpp | 133 Instruction::BinaryOps Opcode = I.getOpcode();
243 Instruction *New = BinaryOperator::Create(Opcode, A, B);
263 static bool LeftDistributesOverRight(Instruction::BinaryOps LOp,
264 Instruction::BinaryOps ROp) {
269 case Instruction::And:
274 case Instruction::Or:
275 case Instruction::Xor:
279 case Instruction::Mul:
284 case Instruction::Add:
285 case Instruction::Sub
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| ConstantProp.cpp | 25 #include "llvm/Instruction.h"
60 std::set<Instruction*> WorkList;
67 Instruction *I = *WorkList.begin();
72 // Add all of the users of this instruction to the worklist, they might
76 WorkList.insert(cast<Instruction>(*UI));
81 // Remove the dead instruction.
|
| /external/llvm/lib/Transforms/Utils/ |
| SimplifyInstructions.cpp | 11 // The analysis is applied to every instruction, and if it simplifies then the
12 // instruction is replaced by the simplification. If you are looking for a pass
13 // that performs serious instruction folding, use the instcombine pass instead.
48 SmallPtrSet<const Instruction*, 8> S1, S2, *ToSimplify = &S1, *Next = &S2;
55 Instruction *I = BI++;
67 Next->insert(cast<Instruction>(*UI));
|
| /external/webkit/Source/JavaScriptCore/interpreter/ |
| Register.h | 45 struct Instruction;
62 Register& operator=(Instruction*);
71 Instruction* vPC() const;
86 Instruction* vPC;
138 ALWAYS_INLINE Register& Register::operator=(Instruction* vPC)
159 ALWAYS_INLINE Instruction* Register::vPC() const
|
| /external/llvm/lib/VMCore/ |
| ConstantFold.cpp | 38 // ConstantFold*Instruction Implementations
90 Instruction::CastOps firstOp = Instruction::CastOps(Op->getOpcode());
91 Instruction::CastOps secondOp = Instruction::CastOps(opc);
104 // the first element. If so, return the appropriate GEP instruction.
221 case Instruction::Or: {
236 case Instruction::And: {
250 case Instruction::LShr: {
272 case Instruction::Shl:
[all...] |
| /dalvik/dx/src/com/android/dx/io/instructions/ |
| FillArrayDataPayloadDecodedInstruction.java | 20 * A decoded Dalvik instruction which contains the payload for
21 * a {@code packed-switch} instruction.
98 throw new UnsupportedOperationException("no index in instruction");
|
| /dalvik/vm/mterp/armv5te/ |
| binop.S | 4 * specifies an instruction that performs "result = r0 op r1".
5 * This could be an ARM instruction or a function call. (If the result
34 GOTO_OPCODE(ip) @ jump to next instruction
|
| binop2addr.S | 4 * that specifies an instruction that performs "result = r0 op r1".
5 * This could be an ARM instruction or a function call. (If the result
32 GOTO_OPCODE(ip) @ jump to next instruction
|
| binopLit8.S | 4 * that specifies an instruction that performs "result = r0 op r1".
5 * This could be an ARM instruction or a function call. (If the result
31 GOTO_OPCODE(ip) @ jump to next instruction
|
| binopWide.S | 4 * specifies an instruction that performs "result = r0-r1 op r2-r3".
5 * This could be an ARM instruction or a function call. (If the result
37 GOTO_OPCODE(ip) @ jump to next instruction
|
| binopWide2addr.S | 4 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
5 * This could be an ARM instruction or a function call. (If the result
34 GOTO_OPCODE(ip) @ jump to next instruction
|
| /dalvik/vm/mterp/armv6t2/ |
| binop2addr.S | 4 * that specifies an instruction that performs "result = r0 op r1".
5 * This could be an ARM instruction or a function call. (If the result
31 GOTO_OPCODE(ip) @ jump to next instruction
|
| binopWide2addr.S | 4 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
5 * This could be an ARM instruction or a function call. (If the result
33 GOTO_OPCODE(ip) @ jump to next instruction
|
| /dalvik/vm/mterp/portable/ |
| entry.cpp | 18 u2 inst; // current instruction
19 /* instruction decoding */
63 FINISH(0); /* fetch and execute first instruction */
|
| /dalvik/vm/mterp/x86-atom/ |
| OP_CMP_LONG.S | 47 FINISH 2 # jump to next instruction
51 FINISH 2 # jump to next instruction
55 FINISH 2 # jump to next instruction
|
| binop2addr.S | 20 * "instr" line to specify an instruction that performs
38 FFETCH_ADV 1, %eax # %eax<- next instruction hi; fetch, advance
43 FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
|
