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  /dalvik/vm/mterp/x86-atom/
OP_MOVE.S 35 FFETCH_ADV 1, %eax # %eax<- next instruction hi; fetch, advance
38 FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
OP_MOVE_16.S 33 FFETCH_ADV 3, %eax # %eax<- next instruction hi; fetch, advance
36 FGETOP_JMP 3, %eax # jump to next instruction; getop, jmp
OP_MOVE_FROM16.S 32 FFETCH_ADV 2, %eax # %eax<- next instruction hi; fetch, advance
35 FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
OP_MOVE_WIDE.S 34 FFETCH_ADV 1, %eax # %eax<- next instruction hi; fetch, advance
37 FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
OP_MOVE_WIDE_16.S 33 FFETCH_ADV 3, %eax # %eax<- next instruction hi; fetch, advance
36 FGETOP_JMP 3, %eax # jump to next instruction; getop, jmp
OP_MOVE_WIDE_FROM16.S 31 FFETCH_ADV 2, %eax # %eax<- next instruction hi; fetch, advance
34 FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
  /external/chromium/sdch/open-vcdiff/src/
decodetable.h 71 // any pending second instruction or unread instruction will still be
84 // Returns the next instruction from the stream of opcodes,
89 // with the corresponding size for the returned instruction;
92 // If the instruction returned is VCD_COPY, *mode will
102 // Puts a single instruction back onto the front of the
103 // instruction stream. The next call to GetNextInstruction()
107 // only rewind one instruction.
encodetable.cc 110 // If that opcode was a single-instruction opcode, this function checks
111 // whether there is a compound (double-instruction) opcode that can
112 // combine that single instruction with the instruction that is now
114 // single-instruction opcode at position last_opcode_index_ will be
115 // overwritten with the new double-instruction opcode.
118 // and a new single-instruction opcode will be appended to
120 // if the opcode does not implicitly give the instruction size.
126 // The function will replace the old opcode 0x02 with the double-instruction
129 // All of the double-instruction opcodes in the standard code tabl
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  /external/llvm/docs/HistoricalNotes/
2000-12-06-EncodingIdea.txt 6 Here's another idea with respect to keeping the common case instruction
9 Instead of encoding an instruction to operate on two register numbers,
2001-02-09-AdveComments.txt 1 Ok, here are my comments and suggestions about the LLVM instruction set.
8 essentially obvious from the instruction type, e.g., in br, it is obvious
16 (e.g., in the br instruction), it doesn't seem to help as much.
37 o There's a trade-off with the cast instruction:
39 valid for the operands of each instruction (you probably have thought
77 concern about an explicit 'icall' instruction?
91 .NET has a tailcall instruction?
101 instruction. (It could be optional so single-threaded codes are
  /external/llvm/include/llvm/MC/
MCCodeEmitter.h 1 //===-- llvm/MC/MCCodeEmitter.h - Instruction Encoding ----------*- C++ -*-===//
23 /// MCCodeEmitter - Generic instruction encoding interface.
  /external/llvm/lib/MC/MCDisassembler/
Disassembler.cpp 86 // Set up the instruction printer.
90 assert(IP && "Unable to create instruction printer!");
133 // LLVMDisasmInstruction() disassembles a single instruction using the
135 // instruction are specified in the parameter Bytes, and contains at least
136 // BytesSize number of bytes. The instruction is at the address specified by
137 // the PC parameter. If a valid instruction can be disassembled its string is
140 // instruction or zero if there was no valid instruction. If this function
  /external/llvm/lib/Target/Mips/
MipsInstrInfo.h 1 //===- MipsInstrInfo.h - Mips Instruction Information -----------*- C++ -*-===//
34 /// instruction info tracks.
86 /// such, whenever a client has an instance of instruction info, it should
91 /// isLoadFromStackSlot - If the specified machine instruction is a direct
94 /// not, return 0. This predicate must return 0 if the instruction has
99 /// isStoreToStackSlot - If the specified machine instruction is a direct
102 /// not, return 0. This predicate must return 0 if the instruction has
147 /// Insert nop instruction when hazard condition is found
  /external/llvm/lib/Target/PTX/
PTXInstrFormats.td 1 //===- PTXInstrFormats.td - PTX Instruction Formats ----------*- tblgen -*-===//
17 : Instruction {
  /external/llvm/test/CodeGen/Generic/
fwdtwice.ll 9 ;; register argument of the "branch-on-register" instruction, i.e.,
11 ;; This produces the bogus output instruction:
  /external/proguard/src/proguard/classfile/instruction/visitor/
AllInstructionVisitor.java 21 package proguard.classfile.instruction.visitor;
29 * This AttributeVisitor lets a given InstructionVisitor visit all Instruction
  /external/proguard/src/proguard/evaluation/
BranchUnit.java 34 * Sets the new instruction offset.
43 * Sets the new instruction offset, depending on the certainty of the
  /external/proguard/src/proguard/optimize/info/
SideEffectInstructionChecker.java 27 import proguard.classfile.instruction.*;
28 import proguard.classfile.instruction.visitor.InstructionVisitor;
33 * This class can tell whether an instruction has any side effects. Return
59 public boolean hasSideEffects(Clazz clazz, Method method, CodeAttribute codeAttribute, int offset, Instruction instruction)
63 instruction.accept(clazz, method, codeAttribute, offset, this);
71 public void visitAnyInstruction(Clazz clazz, Method method, CodeAttribute codeAttribute, int offset, Instruction instruction) {}
  /external/v8/src/mips/
constants-mips.h 40 #define UNSUPPORTED_MIPS() v8::internal::PrintF("Unsupported instruction.\n")
54 // Volume II: The MIPS32 Instruction Set
179 // Instruction bit masks.
197 // MIPS32 Architecture For Programmers, Volume II: The MIPS32 Instruction Set.
511 // A nop instruction. (Encoding of sll 0 0 0).
514 class Instruction {
520 // always the value of the current instruction being executed.
524 // Get the raw instruction bits.
529 // Set the raw instruction bits to value.
534 // Read one particular bit out of the instruction bits
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  /frameworks/compile/libbcc/runtime/lib/
clear_cache.c 20 * It is expected to invalidate the instruction cache for the
28 * Intel processors have a unified instruction and data cache
  /external/webkit/Source/JavaScriptCore/jit/
JITOpcodes32_64.cpp 475 void JIT::emit_op_mov(Instruction* currentInstruction)
489 void JIT::emit_op_end(Instruction* currentInstruction)
497 void JIT::emit_op_jmp(Instruction* currentInstruction)
503 void JIT::emit_op_loop_if_lesseq(Instruction* currentInstruction)
531 void JIT::emitSlow_op_loop_if_lesseq(Instruction* currentInstruction, Vector<SlowCaseEntry>::iterator& iter)
548 void JIT::emit_op_new_object(Instruction* currentInstruction)
553 void JIT::emit_op_check_has_instance(Instruction* currentInstruction)
567 void JIT::emit_op_instanceof(Instruction* currentInstruction)
614 void JIT::emitSlow_op_check_has_instance(Instruction* currentInstruction, Vector<SlowCaseEntry>::iterator& iter)
626 void JIT::emitSlow_op_instanceof(Instruction* currentInstruction, Vector<SlowCaseEntry>::iterator& iter
    [all...]
  /external/llvm/docs/CommandGuide/
llvm-bcanalyzer.pod 101 =item B<Instruction List Bytes>
103 The size, in bytes, of all the instruction lists in all the functions.
172 =item B<Total Instruction Size>
176 =item B<Average Instruction Size>
178 The average number of bytes per instruction across all functions in the bitcode
179 file. This value is computed by dividing Total Instruction Size by Number Of
259 The number of instructions using the long instruction format in the function.
265 =item B<Instruction Size>
269 =item B<Average Instruction Size>
272 value is computed by dividing Instruction Size by Instructions
    [all...]
  /bionic/libc/private/
bionic_atomic_inline.h 35 * on SMP systems emits an appropriate instruction.
60 * The DMB instruction is found in the ARM and Thumb2 instruction sets.
72 * For recent x86, we can use the SSE2 mfence instruction.
91 * For SMP this also includes a memory barrier instruction. On an ARM
  /dalvik/vm/mterp/
NOTES.txt 15 - object allocation (either while executing an instruction that performs
20 (A debugger can in theory cause the interpreter to advance one instruction
36 must not be modified if we abort the instruction with an exception.
44 following instruction is not a "move-result" then the result is ignored,
60 used in a return-object instruction for a brief period. The easiest way
  /dalvik/vm/mterp/armv5te/
entry.S 82 cmp r3, #kSVSNoProfile @ don't profile the next instruction?
83 beq 1f @ intrepret the next instruction
90 /* start executing the instruction at rPC */
93 GOTO_OPCODE(ip) @ jump to next instruction
111 * last instruction causes us to return to whoever called dvmMterpStdRun.

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