| /external/llvm/test/CodeGen/ARM/ |
| arm-frameaddr.ll | 17 declare i8* @llvm.frameaddress(i32) nounwind readnone
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| vpadd.ll | 39 declare <8 x i8> @llvm.arm.neon.vpadd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
40 declare <4 x i16> @llvm.arm.neon.vpadd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
41 declare <2 x i32> @llvm.arm.neon.vpadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
43 declare <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float>, <2 x float>) nounwind readnone
155 declare <4 x i16> @llvm.arm.neon.vpaddls.v4i16.v8i8(<8 x i8>) nounwind readnone
156 declare <2 x i32> @llvm.arm.neon.vpaddls.v2i32.v4i16(<4 x i16>) nounwind readnone
157 declare <1 x i64> @llvm.arm.neon.vpaddls.v1i64.v2i32(<2 x i32>) nounwind readnone
159 declare <4 x i16> @llvm.arm.neon.vpaddlu.v4i16.v8i8(<8 x i8>) nounwind readnone
160 declare <2 x i32> @llvm.arm.neon.vpaddlu.v2i32.v4i16(<4 x i16>) nounwind readnone
161 declare <1 x i64> @llvm.arm.neon.vpaddlu.v1i64.v2i32(<2 x i32>) nounwind readnone
[all...] |
| vqadd.ll | 147 declare <8 x i8> @llvm.arm.neon.vqadds.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
148 declare <4 x i16> @llvm.arm.neon.vqadds.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
149 declare <2 x i32> @llvm.arm.neon.vqadds.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
150 declare <1 x i64> @llvm.arm.neon.vqadds.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
152 declare <8 x i8> @llvm.arm.neon.vqaddu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
153 declare <4 x i16> @llvm.arm.neon.vqaddu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
154 declare <2 x i32> @llvm.arm.neon.vqaddu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
155 declare <1 x i64> @llvm.arm.neon.vqaddu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
157 declare <16 x i8> @llvm.arm.neon.vqadds.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
158 declare <8 x i16> @llvm.arm.neon.vqadds.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
[all...] |
| vqsub.ll | 147 declare <8 x i8> @llvm.arm.neon.vqsubs.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
148 declare <4 x i16> @llvm.arm.neon.vqsubs.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
149 declare <2 x i32> @llvm.arm.neon.vqsubs.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
150 declare <1 x i64> @llvm.arm.neon.vqsubs.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
152 declare <8 x i8> @llvm.arm.neon.vqsubu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
153 declare <4 x i16> @llvm.arm.neon.vqsubu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
154 declare <2 x i32> @llvm.arm.neon.vqsubu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
155 declare <1 x i64> @llvm.arm.neon.vqsubu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
157 declare <16 x i8> @llvm.arm.neon.vqsubs.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
158 declare <8 x i16> @llvm.arm.neon.vqsubs.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
[all...] |
| shuffle.ll | 6 define <8 x i8> @shuf(<8 x i8> %a) nounwind readnone optsize ssp {
13 define <8 x i8> @shuf2(<8 x i8> %a, <8 x i8> %b) nounwind readnone optsize ssp {
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| /external/llvm/test/CodeGen/Mips/ |
| 2009-11-16-CstPoolLoad.ll | 5 define float @h() nounwind readnone {
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| 2008-07-31-fcopysign.ll | 14 tail call float @copysignf( float %i, float %j ) nounwind readnone ; <float>:0 [#uses=1]
18 declare float @copysignf(float, float) nounwind readnone
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| /external/llvm/test/CodeGen/PowerPC/ |
| 2008-05-01-ppc_fp128.ll | 4 define i256 @func(ppc_fp128 %a, ppc_fp128 %b, ppc_fp128 %c, ppc_fp128 %d) nounwind readnone {
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| /external/llvm/test/CodeGen/X86/ |
| 2009-03-03-BitcastLongDouble.ll | 5 define i32 @x(i32 %y) nounwind readnone {
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| 2009-06-07-ExpandMMXBitcast.ll | 3 define i64 @a(i32 %a, i32 %b) nounwind readnone {
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| bit-test-shift.ll | 4 define i32 @x(i32 %t) nounwind readnone ssp {
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| fastcc3struct.ll | 8 define internal fastcc %0 @ReturnBigStruct() nounwind readnone {
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| vec_shuffle-31.ll | 4 define <8 x i16> @shuf3(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
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| win64_params.ll | 5 define i32 @f6(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6) nounwind readnone optsize {
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| 2009-02-12-SpillerBug.ll | 19 %6 = tail call x86_fp80 @copysignl(x86_fp80 0xK00000000000000000000, x86_fp80 %a) nounwind readnone ; <x86_fp80> [#uses=0]
29 declare x86_fp80 @copysignl(x86_fp80, x86_fp80) nounwind readnone
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| coalescer-commute5.ll | 10 %tmp4351 = call <16 x i8> @llvm.x86.sse2.pcmpeq.b( <16 x i8> zeroinitializer, <16 x i8> zeroinitializer ) nounwind readnone ; <<16 x i8>> [#uses=0]
21 declare <16 x i8> @llvm.x86.sse2.pcmpeq.b(<16 x i8>, <16 x i8>) nounwind readnone
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| commute-intrinsic.ll | 10 %tmp11 = tail call <4 x i32> @llvm.x86.sse2.pmadd.wd( <8 x i16> %tmp9, <8 x i16> %tmp6 ) nounwind readnone ; <<4 x i32>> [#uses=1]
15 declare <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16>, <8 x i16>) nounwind readnone
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| umul-with-overflow.ll | 16 define i32 @test2(i32 %a, i32 %b) nounwind readnone {
28 define i32 @test3(i32 %a, i32 %b) nounwind readnone {
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| vec_shift4.ll | 3 define <2 x i64> @shl1(<4 x i32> %r, <4 x i32> %a) nounwind readnone ssp {
16 define <2 x i64> @shl2(<16 x i8> %r, <16 x i8> %a) nounwind readnone ssp {
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| vec_shuffle-35.ll | 10 define <16 x i8> @shuf1(<16 x i8> %T0) nounwind readnone {
16 define <16 x i8> @shuf2(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone {
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| /external/llvm/test/Feature/ |
| metadata.ll | 11 declare void @llvm.zonk(metadata, i64, metadata) nounwind readnone
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| /external/llvm/test/Transforms/InstCombine/ |
| compare-signs.ll | 5 ;define i32 @test1(i32 %a, i32 %b) nounwind readnone {
15 ;define i32 @test2(i32 %a, i32 %b) nounwind readnone {
24 define i32 @test3(i32 %a, i32 %b) nounwind readnone {
42 define i32 @test3i(i32 %a, i32 %b) nounwind readnone {
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| x86-crc32-demanded.ll | 17 declare i64 @llvm.x86.sse42.crc32.64.64(i64, i64) nounwind readnone
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| /external/llvm/test/CodeGen/SystemZ/ |
| 09-Globals.ll | 13 define i64* @foo2() nounwind readnone {
18 define i64* @foo3(i64 %idx) nounwind readnone {
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| /external/llvm/test/CodeGen/Thumb2/ |
| thumb2-cbnz.ll | 4 declare double @floor(double) nounwind readnone
29 %0 = tail call double @floor(double %b) nounwind readnone ; <double> [#uses=0]
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