| /external/llvm/test/Feature/ |
| md_on_instruction.ll | 15 declare void @llvm.dbg.func.start(metadata) nounwind readnone
17 declare void @llvm.dbg.region.end(metadata) nounwind readnone
|
| /external/llvm/test/Transforms/SimplifyCFG/ |
| switch-to-icmp.ll | 3 define zeroext i1 @test1(i32 %x) nounwind readnone ssp noredzone {
23 define zeroext i1 @test2(i32 %x) nounwind readnone ssp noredzone {
|
| /external/llvm/test/CodeGen/ARM/ |
| vpminmax.ll | 66 declare <8 x i8> @llvm.arm.neon.vpmins.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
67 declare <4 x i16> @llvm.arm.neon.vpmins.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
68 declare <2 x i32> @llvm.arm.neon.vpmins.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
70 declare <8 x i8> @llvm.arm.neon.vpminu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
71 declare <4 x i16> @llvm.arm.neon.vpminu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
72 declare <2 x i32> @llvm.arm.neon.vpminu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
74 declare <2 x float> @llvm.arm.neon.vpmins.v2f32(<2 x float>, <2 x float>) nounwind readnone
139 declare <8 x i8> @llvm.arm.neon.vpmaxs.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
140 declare <4 x i16> @llvm.arm.neon.vpmaxs.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
141 declare <2 x i32> @llvm.arm.neon.vpmaxs.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
[all...] |
| vcvt.ll | 99 declare <2 x i32> @llvm.arm.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float>, i32) nounwind readnone
100 declare <2 x i32> @llvm.arm.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float>, i32) nounwind readnone
101 declare <2 x float> @llvm.arm.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone
102 declare <2 x float> @llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone
136 declare <4 x i32> @llvm.arm.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float>, i32) nounwind readnone
137 declare <4 x i32> @llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float>, i32) nounwind readnone
138 declare <4 x float> @llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone
139 declare <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone
157 declare <4 x float> @llvm.arm.neon.vcvthf2fp(<4 x i16>) nounwind readnone
158 declare <4 x i16> @llvm.arm.neon.vcvtfp2hf(<4 x float>) nounwind readnone
[all...] |
| vqshl.ll | 339 declare <8 x i8> @llvm.arm.neon.vqshifts.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
340 declare <4 x i16> @llvm.arm.neon.vqshifts.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
341 declare <2 x i32> @llvm.arm.neon.vqshifts.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
342 declare <1 x i64> @llvm.arm.neon.vqshifts.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
344 declare <8 x i8> @llvm.arm.neon.vqshiftu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
345 declare <4 x i16> @llvm.arm.neon.vqshiftu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
346 declare <2 x i32> @llvm.arm.neon.vqshiftu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
347 declare <1 x i64> @llvm.arm.neon.vqshiftu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
349 declare <8 x i8> @llvm.arm.neon.vqshiftsu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
350 declare <4 x i16> @llvm.arm.neon.vqshiftsu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
[all...] |
| vminmax.ll | 129 declare <8 x i8> @llvm.arm.neon.vmins.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
130 declare <4 x i16> @llvm.arm.neon.vmins.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
131 declare <2 x i32> @llvm.arm.neon.vmins.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
133 declare <8 x i8> @llvm.arm.neon.vminu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
134 declare <4 x i16> @llvm.arm.neon.vminu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
135 declare <2 x i32> @llvm.arm.neon.vminu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
137 declare <2 x float> @llvm.arm.neon.vmins.v2f32(<2 x float>, <2 x float>) nounwind readnone
139 declare <16 x i8> @llvm.arm.neon.vmins.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
140 declare <8 x i16> @llvm.arm.neon.vmins.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
141 declare <4 x i32> @llvm.arm.neon.vmins.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
[all...] |
| vqdmul.ll | 41 define arm_aapcs_vfpcc <8 x i16> @test_vqdmulhQ_lanes16(<8 x i16> %arg0_int16x8_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {
50 define arm_aapcs_vfpcc <4 x i32> @test_vqdmulhQ_lanes32(<4 x i32> %arg0_int32x4_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {
59 define arm_aapcs_vfpcc <4 x i16> @test_vqdmulh_lanes16(<4 x i16> %arg0_int16x4_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {
68 define arm_aapcs_vfpcc <2 x i32> @test_vqdmulh_lanes32(<2 x i32> %arg0_int32x2_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {
77 declare <4 x i16> @llvm.arm.neon.vqdmulh.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
78 declare <2 x i32> @llvm.arm.neon.vqdmulh.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
80 declare <8 x i16> @llvm.arm.neon.vqdmulh.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
81 declare <4 x i32> @llvm.arm.neon.vqdmulh.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
119 define arm_aapcs_vfpcc <8 x i16> @test_vqRdmulhQ_lanes16(<8 x i16> %arg0_int16x8_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {
128 define arm_aapcs_vfpcc <4 x i32> @test_vqRdmulhQ_lanes32(<4 x i32> %arg0_int32x4_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {
[all...] |
| avoid-cpsr-rmw.ll | 6 define i32 @t(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone {
|
| neon_shift.ll | 11 declare <4 x i16> @llvm.arm.neon.vqrshiftns.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
|
| /external/llvm/test/CodeGen/Mips/ |
| select.ll | 7 define i32 @sel1(i32 %s, i32 %f0, i32 %f1) nounwind readnone {
16 define float @sel2(i32 %s, float %f0, float %f1) nounwind readnone {
25 define double @sel2_1(i32 %s, double %f0, double %f1) nounwind readnone {
34 define float @sel3(float %f0, float %f1, float %f2, float %f3) nounwind readnone {
45 define float @sel4(float %f0, float %f1, float %f2, float %f3) nounwind readnone {
56 define float @sel5(float %f0, float %f1, float %f2, float %f3) nounwind readnone {
67 define double @sel5_1(double %f0, double %f1, float %f2, float %f3) nounwind readnone {
78 define double @sel6(double %f0, double %f1, double %f2, double %f3) nounwind readnone {
89 define double @sel7(double %f0, double %f1, double %f2, double %f3) nounwind readnone {
100 define double @sel8(double %f0, double %f1, double %f2, double %f3) nounwind readnone {
[all...] |
| 2008-08-08-bswap.ll | 12 declare i32 @llvm.bswap.i32(i32) nounwind readnone
|
| 2008-08-08-ctlz.ll | 12 declare i32 @llvm.ctlz.i32(i32) nounwind readnone
|
| /external/llvm/test/CodeGen/X86/ |
| avx-256-logic.ll | 4 define <4 x double> @andpd256(<4 x double> %y, <4 x double> %x) nounwind uwtable readnone ssp {
14 define <4 x double> @andpd256fold(<4 x double> %y) nounwind uwtable readnone ssp {
23 define <8 x float> @andps256(<8 x float> %y, <8 x float> %x) nounwind uwtable readnone ssp {
33 define <8 x float> @andps256fold(<8 x float> %y) nounwind uwtable readnone ssp {
42 define <4 x double> @xorpd256(<4 x double> %y, <4 x double> %x) nounwind uwtable readnone ssp {
52 define <4 x double> @xorpd256fold(<4 x double> %y) nounwind uwtable readnone ssp {
61 define <8 x float> @xorps256(<8 x float> %y, <8 x float> %x) nounwind uwtable readnone ssp {
71 define <8 x float> @xorps256fold(<8 x float> %y) nounwind uwtable readnone ssp {
80 define <4 x double> @orpd256(<4 x double> %y, <4 x double> %x) nounwind uwtable readnone ssp {
90 define <4 x double> @orpd256fold(<4 x double> %y) nounwind uwtable readnone ssp
[all...] |
| sse41.ll | 35 %6 = tail call <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8> %5) nounwind readnone
52 %2 = tail call <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16> %1) nounwind readnone ; <<4 x i32>> [#uses=1]
72 %3 = tail call <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8> %2) nounwind readnone ; <<2 x i64>> [#uses=1]
84 declare <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8>) nounwind readnone
85 declare <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16>) nounwind readnone
86 declare <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8>) nounwind readnone
154 %tmp1 = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %t1, <4 x float> %t2, i32 1) nounwind readnone
163 declare <4 x float> @llvm.x86.sse41.insertps(<4 x float>, <4 x float>, i32) nounwind readnone
187 %tmp1 = call i32 @llvm.x86.sse41.ptestz(<4 x float> %t1, <4 x float> %t2) nounwind readnone
199 %tmp1 = call i32 @llvm.x86.sse41.ptestc(<4 x float> %t1, <4 x float> %t2) nounwind readnone
[all...] |
| 3addr-or.ll | 4 define i32 @test1(i32 %x) nounwind readnone ssp {
31 define void @test3(i32 %x, i32* %P) nounwind readnone ssp {
42 define i32 @test4(i32 %a, i32 %b) nounwind readnone ssp {
|
| mmx-vzmovl-2.ll | 7 declare x86_mmx @llvm.x86.mmx.psrli.q(x86_mmx, i32) nounwind readnone
19 %3 = call x86_mmx @llvm.x86.mmx.psrli.q(x86_mmx %0, i32 32) nounwind readnone ; <<1 x i64>> [#uses=1]
24 %4 = call x86_mmx @llvm.x86.mmx.psrli.q(x86_mmx %tmp5, i32 32) nounwind readnone ; <<1 x i64>> [#uses=1]
|
| vec_compare-2.ll | 3 declare <4 x float> @llvm.x86.sse41.blendvps(<4 x float>, <4 x float>, <4 x float>) nounwind readnone
5 declare <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32>, <4 x i32>) nounwind readnone
7 declare <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32>, <4 x i32>) nounwind readnone
|
| /external/llvm/test/Transforms/InstCombine/ |
| bit-checks.ll | 17 define i32 @main2(i32 %argc, i8** nocapture %argv) nounwind readnone ssp {
33 define i32 @main3(i32 %argc, i8** nocapture %argv) nounwind readnone ssp {
44 define i32 @main3b(i32 %argc, i8** nocapture %argv) nounwind readnone ssp {
56 nounwind readnone ssp {
68 define i32 @main3c(i32 %argc, i8** nocapture %argv) nounwind readnone ssp {
79 define i32 @main3d(i32 %argc, i8** nocapture %argv) nounwind readnone ssp {
91 nounwind readnone ssp {
103 define i32 @main4(i32 %argc, i8** nocapture %argv) nounwind readnone ssp {
114 define i32 @main4b(i32 %argc, i8** nocapture %argv) nounwind readnone ssp {
126 nounwind readnone ssp
[all...] |
| /external/llvm/test/CodeGen/CellSPU/ |
| extract_elt.ll | 207 define i8 @extract_varadic_i8(i32 %i) nounwind readnone {
213 define i8 @extract_varadic_i8_1(<16 x i8> %v, i32 %i) nounwind readnone {
219 define i16 @extract_varadic_i16(i32 %i) nounwind readnone {
225 define i16 @extract_varadic_i16_1(<8 x i16> %v, i32 %i) nounwind readnone {
231 define i32 @extract_varadic_i32(i32 %i) nounwind readnone {
237 define i32 @extract_varadic_i32_1(<4 x i32> %v, i32 %i) nounwind readnone {
243 define float @extract_varadic_f32(i32 %i) nounwind readnone {
249 define float @extract_varadic_f32_1(<4 x float> %v, i32 %i) nounwind readnone {
255 define i64 @extract_varadic_i64(i32 %i) nounwind readnone {
261 define i64 @extract_varadic_i64_1(<2 x i64> %v, i32 %i) nounwind readnone {
[all...] |
| /external/llvm/test/CodeGen/Thumb2/ |
| bfi.ll | 19 define i32 @f2(i32 %A, i32 %B) nounwind readnone optsize {
30 define i32 @f3(i32 %A, i32 %B) nounwind readnone optsize {
53 define i32 @f5(i32 %a, i32 %b) nounwind readnone {
|
| /external/clang/test/CodeGen/ |
| struct-passing.c | 19 // CHECK: declare i32 @f0() readnone
|
| /external/llvm/test/Analysis/TypeBasedAliasAnalysis/ |
| functionattrs.ll | 5 ; Add the readnone attribute, since the only access is a store which TBAA
12 ; CHECK: define void @test0_yes(i32* nocapture %p) nounwind readnone {
46 ; CHECK: define void @test2_yes(i8* nocapture %p, i8* nocapture %q, i64 %n) nounwind readnone {
60 ; CHECK: define i32 @test3_yes(i8* nocapture %p) nounwind readnone {
|
| /external/llvm/test/CodeGen/Blackfin/ |
| ctlz64.ll | 15 declare i64 @llvm.cttz.i64(i64) nounwind readnone
|
| /external/llvm/test/CodeGen/MSP430/ |
| 2009-11-05-8BitLibcalls.ll | 8 define signext i8 @foo(i8 signext %_si1, i8 signext %_si2) nounwind readnone {
|
| /external/llvm/test/CodeGen/PowerPC/ |
| stubs.ll | 2 define ppc_fp128 @test1(i64 %X) nounwind readnone {
|
