| /external/qemu/target-arm/ |
| cpu.h | 192 * values corresponding to the ARM "Standard FPSCR Value", ie
195 * as controlled by the standard FPSCR value rather than the FPSCR.
198 * say that the FPSCR cumulative exception flags are the logical
201 * an explicit FPSCR read.
331 /* Return the current FPSCR value. */
|
| machine.c | 75 /* TODO: Should use proper FPSCR access functions. */
191 /* TODO: Should use proper FPSCR access functions. */
|
| /bionic/libc/kernel/arch-sh/asm/ |
| processor_64.h | 77 unsigned int fpscr; member in struct:sh_fpu_hard_struct
|
| /external/clang/test/Sema/ |
| statements.c | 40 switch (env->fpscr) // expected-error {{use of undeclared identifier 'env'}}
|
| /external/llvm/test/CodeGen/ARM/ |
| fpcmp-opt.ll | 20 ; NAN: vmrs apsr_nzcv, fpscr
|
| /external/qemu/gdb-xml/ |
| arm-vfp3.xml | 43 <reg name="fpscr" bitsize="32" type="int" group="float"/>
|
| power-fpu.xml | 43 <reg name="fpscr" bitsize="32" group="float"/>
|
| arm-neon.xml | 86 <reg name="fpscr" bitsize="32" type="int" group="float"/>
|
| /external/valgrind/main/coregrind/m_dispatch/ |
| dispatch-ppc64-linux.S | 191 /* 96(sp) used later to check FPSCR[RM] */
192 /* 88(sp) used later to load fpscr with zero */
221 mtfsf 0xFF,3 /* fpscr = lo32 of f3 */
272 144(r1) (=var space for FPSCR[RM])
339 144(r1) (=var space for FPSCR[RM])
430 VSCR or FPSCR. */
432 /* Set fpscr back to a known state, since vex-generated code
433 may have messed with fpscr[rm]. */
439 mtfsf 0xFF,3 /* fpscr = f3 */
|
| dispatch-ppc32-linux.S | 177 /* 32(sp) used later to check FPSCR[RM] */
185 /* 20(sp) used later to load fpscr with zero */
215 mtfsf 0xFF,3 /* fpscr = f3 */
401 VSCR or FPSCR. */
409 /* Set fpscr back to a known state, since vex-generated code
410 may have messed with fpscr[rm]. */
416 mtfsf 0xFF,3 /* fpscr = f3 */
|
| dispatch-arm-linux.S | 59 /* set FPSCR to vex-required default value */
61 fmxr fpscr, r4
216 FPSCR in ways we don't expect. */
217 fmrx r4, fpscr
|
| dispatch-ppc32-aix5.S | 236 mtfsf 0xFF,3 /* fpscr = f3 */
417 VSCR or FPSCR. */
425 /* Set fpscr back to a known state, since vex-generated code
426 may have messed with fpscr[rm]. */
430 mtfsf 0xFF,3 /* fpscr = f3 */
|
| dispatch-ppc64-aix5.S | 225 mtfsf 0xFF,3 /* fpscr = f3 */
403 VSCR or FPSCR. */
405 /* Set fpscr back to a known state, since vex-generated code
406 may have messed with fpscr[rm]. */
410 mtfsf 0xFF,3 /* fpscr = f3 */
|
| /external/llvm/lib/Target/ARM/ |
| ARMInstrVFP.td | 257 let Defs = [FPSCR] in {
286 } // Defs = [FPSCR]
306 let Defs = [FPSCR] in {
347 } // Defs = [FPSCR]
714 // And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR.
715 let Uses = [FPSCR] in {
[all...] |
| ARMRegisterInfo.td | 187 def FPSCR : ARMReg<3, "fpscr">;
|
| /bionic/libc/arch-arm/include/machine/ |
| setjmp.h | 54 * FPSCR saved because GLibc does saves it too.
|
| /external/valgrind/main/docs/internals/ |
| register-uses.txt | 90 fpscr
163 fpscr
|
| /external/v8/test/cctest/ |
| test-disasm-arm.cc | 514 "eee15a10 vmsr FPSCR, r5");
516 "5ee1aa10 vmsrpl FPSCR, r10");
518 "eee1fa10 vmsr FPSCR, APSR");
520 "eef15a10 vmrs r5, FPSCR");
522 "aef1aa10 vmrsge r10, FPSCR");
524 "eef1fa10 vmrs APSR, FPSCR");
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.h | 142 /// OUTFLAG = MFFS F8RC - This moves the FPSCR (not modelled) into the
146 /// OUTFLAG = MTFSB0 INFLAG - This clears a bit in the FPSCR.
149 /// OUTFLAG = MTFSB1 INFLAG - This sets a bit in the FPSCR.
154 /// FPSCR-setting instructions.
157 /// MTFSF = F8RC, INFLAG - This moves the register into the FPSCR.
|
| /external/valgrind/main/auxprogs/ |
| ppcfround.c | 13 UInt fpscr; member in struct:__anon12058
106 (r.cr >> 24) & 0xF, (r.fpscr >> 12) & 0x1F);
156 result.fpscr = foo.fpscr_after; \
|
| /external/kernel-headers/original/asm-arm/ |
| user.h | 90 unsigned long fpscr; member in struct:user_vfp
|
| /external/llvm/test/MC/ARM/ |
| thumb2.s | 178 @ CHECK: vmrs r0, fpscr @ encoding: [0xf1,0xee,0x10,0x0a]
179 vmrs r0, fpscr
185 @ CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
186 vmsr fpscr, r0
|
| /prebuilt/android-arm/gdbserver/ |
| gdbserver | |
| /system/core/debuggerd/arm/ |
| machine.c | 247 _LOG(tfd, only_in_tombstone, " scr %08lx\n\n", vfp_regs.fpscr);
|
| /external/qemu/ |
| gdbstub.c | 668 GET_REG32(0); /* fpscr */
713 /* fpscr */
1093 GET_REGL(env->fregs[(n - 25) + ((env->fpscr & FPSCR_FR) ? 16 : 0)]);
1108 case 24: GET_REGL(env->fpscr);
1133 env->fregs[(n - 25) + ((env->fpscr & FPSCR_FR) ? 16 : 0)] = tmp;
1150 case 24: env->fpscr = tmp;
[all...] |
