| /external/llvm/lib/Target/CellSPU/ |
| SPURegisterInfo.h | 86 Converts a regiser displacement load/store into a register-indexed
|
| /external/llvm/lib/Target/X86/ |
| X86RegisterInfo.h | 97 /// getReservedRegs - Returns a bitset indexed by physical register number
|
| /external/mesa3d/docs/ |
| README.WINDML | 96 - Color Indexed management is only in 8 bits
|
| /external/neven/FaceRecEm/common/src/b_FDSDK/ |
| DCR.h | 127 /** extracts information about indexed node */
|
| /external/openssl/crypto/bn/ |
| bn_kron.c | 69 /* In 'tab', only odd-indexed entries are relevant:
|
| /external/oprofile/libpp/ |
| profile_spec.h | 27 * indexed by tag_name.
|
| /external/qemu/distrib/zlib-1.2.3/ |
| zutil.h | 53 extern const char * const z_errmsg[10]; /* indexed by 2-zlib_error */
|
| /external/skia/gpu/include/ |
| GrContext.h | 133 * Returns true if the specified use of an indexed texture is supported.
333 * are drawn non-indexed.
364 * @param indices optional, pass NULL for non-indexed drawing. If
365 * present supplies indices for indexed drawing
|
| GrDrawTarget.h | 607 * indices) to the draw target. When indexed drawing the indices and vertices
645 * to be filled by caller. The next indexed draw will read from
724 * Sets source of index data for the next indexed draw. Array must contain
744 * Sets source of index data for the next indexed draw. Data does not have
748 * before indexed draw call.
753 * Draws indexed geometry using the current state and current vertex / index
772 * Draws non-indexed geometry using the current state and current vertex
[all...] |
| /external/skia/gpu/src/ |
| GrGpuGL.h | 112 void setBuffers(bool indexed,
|
| /external/skia/include/core/ |
| SkAdvancedTypefaceMetrics.h | 111 // This is indexed by glyph id.
|
| /external/srec/tools/grxmlcompile/ |
| hashmap.cpp | 5 * A doubly indexed map class using two maps.
|
| /external/srec/tools/thirdparty/OpenFst/fst/lib/ |
| heap.h | 74 // indexed by the key. The position gives the position in the heap array.
|
| /external/v8/test/mjsunit/regress/ |
| regress-969.js | 103 // Assignment, compound assignment, and pre and post-increment of indexed
|
| /external/webkit/Source/JavaScriptCore/tests/mozilla/ecma_3/Function/ |
| arguments-001.js | 93 * Note that only callee and length can be overridden, so deleting an indexed
|
| /external/webkit/Source/JavaScriptCore/tests/mozilla/js1_5/Regress/ |
| regress-57043.js | 26 * We check that object properties may be indexed by signed
|
| /external/webkit/Source/WebCore/bindings/v8/custom/ |
| V8StorageCustom.cpp | 42 // Get an array containing the names of indexed properties in a collection.
|
| /external/webkit/Source/WebCore/platform/graphics/win/ |
| QTDecompressionSession.cpp | 95 // Indexed pixel formats get a depth of 1 through 8, depending on
|
| /external/zlib/ |
| zutil.h | 43 extern const char * const z_errmsg[10]; /* indexed by 2-zlib_error */
|
| /frameworks/base/opengl/java/android/opengl/ |
| Visibility.java | 27 * is specified as an indexed triangle list.
|
| /external/llvm/lib/Target/ARM/ |
| README.txt | 278 Pre-/post- indexed load / stores:
280 1) We should not make the pre/post- indexed load/store transform if the base ptr
301 2) Consider spliting a indexed load / store into a pair of add/sub + load/store
304 3) Enhance LSR to generate more opportunities for indexed ops.
306 4) Once we added support for multiple result patterns, write indexed loads
309 5) Use VLDM / VSTM to emulate indexed FP load / store.
408 1. Teach LSR about pre- and post- indexed ops to allow iv increment be merged
|
| /dalvik/dx/src/com/android/dx/ssa/back/ |
| FirstFitLocalCombiningAllocator.java | 58 /** indexed by SSA reg; the set of SSA regs we've mapped */
876 * @param categoriesForIndex {@code non-null;} indexed by source index;
878 * @param outMovesRequired {@code non-null;} an output parameter indexed by
907 * @param categoriesForIndex {@code non-null;} indexed by source index;
909 * @param outMovesRequired {@code non-null;} an output parameter indexed by
[all...] |
| /cts/tools/dasm/src/java_cup/runtime/ |
| lr_parser.java | 145 * This table contains one entry per production and is indexed by
156 * indexed by state and terminal number indicating what action is to
159 * States are indexed using the first dimension, however, the entries for
174 * table is indexed by state and non-terminal number and contains
175 * state numbers. States are indexed using the first dimension, however,
181 * then indexed by that state and the LHS of the reducing production to
264 * subclass). Actions are indexed by an internal action number assigned
378 * rows, one per state (rows are indexed directly by state number).
433 * rows, one per state (rows are indexed directly by state number).
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 457 // indexed memory ops).
634 /// MemIndexedMode enum - This enum defines the load / store indexed
649 /// producing a chain, pre-indexed load produces two values
651 /// computation); a pre-indexed store produces one value (result
657 /// producing a chain, post-indexed load produces two values
659 /// computation); a post-indexed store produces one value (the
[all...] |
| /external/apache-xml/src/main/java/org/apache/xml/dtm/ref/sax2dtm/ |
| SAX2RTFDTM.java | 275 * RTFs will not be indexed, so I can simply panic if that case
281 throw new java.lang.NullPointerException("Coding error; Don't try to mark/rewind an indexed DTM");
|
