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  /external/llvm/include/llvm/CodeGen/
ISDOpcodes.h 332 // SetCC operator - This evaluates to a true value iff the condition is
337 SETCC,
492 // compare, rather than as a combined SetCC node. The operands in order are
    [all...]
SelectionDAG.h 558 /// getSetCC - Helper function to make it easier to build SetCC's if you just
563 return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond));
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  /external/llvm/lib/Target/PowerPC/
PPCISelDAGToDAG.cpp 573 /// associated with the SetCC condition, and whether or not the field is
617 // We can codegen setcc op, imm very efficiently compared to a brcond.
619 // setcc op, 0
649 } else if (Imm == ~0U) { // setcc op, -1
819 case ISD::SETCC:
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  /external/llvm/lib/Target/X86/
X86ISelLowering.cpp 223 // X86 is weird, it always uses i8 for shift amounts and setcc results.
453 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
454 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
455 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
456 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
457 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
458 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
461 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
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X86ISelLowering.h 89 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
91 SETCC,
93 // Same as SETCC except it's materialized with a sbb and the value is all
97 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
567 /// getSetCCResultType - Return the ISD::SETCC ValueType
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  /external/icu4c/tools/gennorm2/
gennorm2.cpp 220 builder.setCC(c, (uint8_t)value);
  /external/llvm/lib/CodeGen/SelectionDAG/
LegalizeIntegerTypes.cpp 67 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
470 assert(isTypeLegal(SVT) && "Illegal SetCC type!");
473 // Get the SETCC result using the canonical SETCC type.
474 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, SVT, N->getOperand(0),
480 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
726 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
759 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
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SelectionDAGBuilder.h 209 // CC - the condition code to use for the case block's setcc node
215 // TrueBB/FalseBB - the block to branch to if the setcc is true/false.
217 // ThisBB - the block into which to emit the code for the setcc and branches
TargetLowering.cpp     [all...]
LegalizeDAG.cpp 45 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
46 /// will attempt merge setcc and brc instructions into brcc's.
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SelectionDAG.cpp 224 /// 'op' is a valid SetCC operation.
244 default: llvm_unreachable("Illegal integer setcc operation!");
265 // Cannot fold a signed integer setcc with an unsigned integer setcc.
275 // Canonicalize illegal integer setcc's.
289 // Cannot fold a signed setcc with an unsigned setcc.
295 // Canonicalize illegal integer setcc's.
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  /external/llvm/lib/Target/SystemZ/
SystemZISelLowering.cpp 116 setOperationAction(ISD::SETCC, MVT::i32, Expand);
117 setOperationAction(ISD::SETCC, MVT::i64, Expand);
118 setOperationAction(ISD::SETCC, MVT::f32, Expand);
119 setOperationAction(ISD::SETCC, MVT::f64, Expand);
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  /frameworks/base/core/java/com/google/android/mms/pdu/
SendReq.java 145 public void setCc(EncodedStringValue[] value) {
  /external/llvm/lib/Target/Mips/
MipsISelLowering.cpp 75 // setcc operations results (slt, sgt, ...).
96 // Used by legalize types to correctly generate the setcc result.
97 // Without this, every float setcc comes with a AND/OR with the result,
100 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
183 setTargetDAGCombine(ISD::SETCC);
443 // Creates and returns an FPCmp node from a setcc node.
444 // Returns Op if setcc is not a floating point comparison.
446 // must be a SETCC node
447 if (Op.getOpcode() != ISD::SETCC)
508 case ISD::SETCC
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  /external/v8/src/arm/
macro-assembler-arm.cc     [all...]
regexp-macro-assembler-arm.cc 295 __ sub(r1, r1, r0, SetCC); // Length of capture.
398 __ sub(r1, r1, r0, SetCC); // Length to check.
636 __ sub(r0, sp, r0, SetCC);
689 __ sub(r2, r2, Operand(1), SetCC);
    [all...]
lithium-codegen-arm.cc 160 __ sub(r0, r0, Operand(1), SetCC);
845 __ rsb(dividend, dividend, Operand(0), SetCC);
956 __ sub(scratch2, left, scratch, SetCC);
    [all...]
stub-cache-arm.cc     [all...]
  /external/llvm/lib/Target/Blackfin/
BlackfinInstrInfo.td 562 multiclass SETCC<PatFrag opnode, PatFrag invnode, string cond, string suf=";"> {
580 defm SETEQ : SETCC<seteq, setne, "==">;
581 defm SETLT : SETCC<setlt, setge, "<">;
582 defm SETLE : SETCC<setle, setgt, "<=">;
583 defm SETULT : SETCC<setult, setuge, "<", " (iu);">;
584 defm SETULE : SETCC<setule, setugt, "<=", " (iu);">;
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  /external/llvm/lib/Target/CellSPU/
SPUISelLowering.cpp 312 setOperationAction(ISD::SETCC, MVT::i8, Legal);
313 setOperationAction(ISD::SETCC, MVT::i16, Legal);
314 setOperationAction(ISD::SETCC, MVT::i32, Legal);
315 setOperationAction(ISD::SETCC, MVT::i64, Legal);
316 setOperationAction(ISD::SETCC, MVT::f64, Custom);
497 // Return the Cell SPU's SETCC result type
501 // i8, i16 and i32 are valid SETCC result types
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  /external/llvm/test/CodeGen/Generic/
select.ll 22 ; A SetCC whose result is used should produce instructions to
  /external/llvm/test/CodeGen/X86/
cmov.ll 118 ; Should compile to setcc | -2.
  /external/llvm/lib/Target/MBlaze/
MBlazeISelLowering.cpp 60 // setcc operations results (slt, sgt, ...).
137 // Used by legalize types to correctly generate the setcc result.
138 // Without this, every float setcc comes with a AND/OR with the result,
141 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
361 // setcc r1, r2, r3
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  /external/llvm/lib/Target/MSP430/
MSP430ISelLowering.cpp 114 setOperationAction(ISD::SETCC, MVT::i8, Custom);
115 setOperationAction(ISD::SETCC, MVT::i16, Custom);
187 case ISD::SETCC: return LowerSETCC(Op, DAG);
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  /external/v8/src/ia32/
disasm-ia32.cc 342 int SetCC(byte* data);
639 int DisassemblerIA32::SetCC(byte* data) {
991 data += SetCC(data);
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