| /system/core/libpixelflinger/codeflinger/ |
| load_store.cpp | 121 MOV(AL, 0, d.reg, reg_imm(s, LSR, l)); // component = packed >> l;
145 MOV(AL, 0, d.reg, reg_imm(s, LSR, l)); // component = packed >> l;
223 ORR(AL, 0, d, d, reg_imm(d, LSR, sbits));
340 MOV(AL, 0, ireg, reg_imm(s.reg, LSR, sl));
346 SUB(AL, 0, ireg, s.reg, reg_imm(s.reg, LSR, dbits));
348 if (shift>0) ADD(AL, 0, ireg, ireg, reg_imm(dither.reg, LSR, shift));
357 MOV(AL, 0, ireg, reg_imm(s.reg, LSR, shift));
365 MOV(AL, 0, d.reg, reg_imm(s.reg, LSR, shift));
367 ORR(AL, 0, d.reg, d.reg, reg_imm(s.reg, LSR, shift));
374 MOV(AL, 0, d.reg, reg_imm(s.reg, LSR, shift))
[all...] |
| texturing.cpp | 102 MOV(AL, 0, end, reg_imm(parts.count.reg, LSR, 16));
166 reg_imm(parts.iterated.reg, LSR, 16));
822 MOV(AL, 0, u, reg_imm(u, LSR, adjust));
837 MOV(AL, 0, u, reg_imm(u, LSR, adjust));
851 MOV(AL, 0, u, reg_imm(u, LSR, adjust));
[all...] |
| /frameworks/base/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/ |
| convolve_opt.s | 69 MOV r5, r5, LSR #16 @extract_h(s)
106 MOV r8, r8, LSR #16 @extract_h(s)
144 MOV r8, r8, LSR #16 @extract_h(s)
172 MOV r5, r5, LSR #16 @extract_h(s)
|
| /frameworks/base/media/libstagefright/codecs/amrwbenc/src/asm/ARMV7/ |
| convolve_neon.s | 66 MOV r5, r5, LSR #16 @extract_h(s)
102 MOV r8, r8, LSR #16 @extract_h(s)
141 MOV r8, r8, LSR #16 @extract_h(s)
165 MOV r5, r5, LSR #16 @extract_h(s)
|
| /frameworks/base/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/vc/m4p10/src/ |
| armVCM4P10_InterpolateLuma_HalfHor4x4_unsafe_s.s | 137 AND Acc1, r0x00ff00ff, Acc1, LSR #5
138 AND Acc0, r0x00ff00ff, Acc0, LSR #5
159 AND Acc3, r0x00ff00ff, Acc3, LSR #5
160 AND Acc2, r0x00ff00ff, Acc2, LSR #5
|
| armVCM4P10_InterpolateLuma_HalfVer4x4_unsafe_s.s | 163 AND Acc1, r0x00ff00ff, Acc1, LSR #5 ;// [0 a3 0 a1]
164 AND Acc0, r0x00ff00ff, Acc0, LSR #5 ;// [0 a2 0 a0]
166 AND Acc3, r0x00ff00ff, Acc3, LSR #5 ;// [0 b3 0 b1]
167 AND Acc2, r0x00ff00ff, Acc2, LSR #5 ;// [0 b2 0 b0]
|
| armVCM4P10_Interpolate_Chroma_s.s | 175 MOV OutRow00, OutRow00, LSR #6
176 MOV OutRow01, OutRow01, LSR #6
202 MOV OutRow10, OutRow10, LSR #6
203 MOV OutRow11, OutRow11, LSR #6
|
| omxVCM4P10_FilterDeblockingChroma_VerEdge_I_s.s | 244 MOVEQ filt, filt, LSR #16
386 MOV t1, Q_0, LSR #24
388 MOV t1, P_0, LSR #24
391 MOV t1, Q_0, LSR #16
393 MOV t1, P_0, LSR #16
396 MOV t1, P_0, LSR #8
399 MOV t1, Q_0, LSR #8
|
| armVCM4P10_InterpolateLuma_HalfDiagHorVer4x4_unsafe_s.s | 271 MOV Acc0, Acc0, LSR #10
273 MOV Acc1, Acc1, LSR #10
275 MOV Acc2, Acc2, LSR #10
277 MOV Acc3, Acc3, LSR #10
|
| armVCM4P10_InterpolateLuma_HalfDiagVerHor4x4_unsafe_s.s | 255 MOV Acc0, Acc0, LSR #10
256 MOV Acc1, Acc1, LSR #10
257 MOV Acc2, Acc2, LSR #10
258 MOV Acc3, Acc3, LSR #10
|
| armVCM4P10_DecodeCoeffsToPair_s.s | 124 MOVS TotalCoeff, Symbol, LSR #2
191 MOVS T1, Symbol, LSR #1
299 MOV T2, T2, LSR #8
|
| omxVCM4P10_FilterDeblockingLuma_VerEdge_I_s.s | 496 MOV t4, tunpk1, LSR #16
497 MOV t0, tunpk9, LSR #16
502 MOV t4, tunpk2, LSR #16
503 MOV t0, tunpk3, LSR #16
|
| /frameworks/base/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/vc/m4p2/src/ |
| armVCM4P2_DecodeVLCZigzag_AC_unsafe_s.s | 141 LSR Escape,Escape,#25
230 LSR storeRun,packRetIndex,#7 ;// Get Run Value from Packed index
237 LSR storeLevel,storeLevel,#2 ;// Level value
298 LSR Last,Last,#1
|
| omxVCM4P2_DecodeVLCZigzag_IntraDCVLC_s.s | 167 CMP DCVal,powOfSize,LSR #1 ;// Compare DCVal with powOfSize/2
|
| /frameworks/base/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p2/src/ |
| armVCM4P2_DecodeVLCZigzag_AC_unsafe_s.s | 141 LSR Escape,Escape,#25
230 LSR storeRun,packRetIndex,#7 ;// Get Run Value from Packed index
237 LSR storeLevel,storeLevel,#2 ;// Level value
298 LSR Last,Last,#1
|
| omxVCM4P2_DecodeVLCZigzag_IntraDCVLC_s.s | 167 CMP DCVal,powOfSize,LSR #1 ;// Compare DCVal with powOfSize/2
|
| /external/tremolo/Tremolo/ |
| dpen.s | 98 MOVS r0, r0, LSR #1 @ r0 = lok>>1 C = bottom bit
123 MOVS r0, r0, LSR #1 @ r0 = lok>>1 C = bottom bit
142 LDRB r14,[r12,r14,LSR #7] @ r14= t[chase+bit+1+(!bit || t[chase]0x0x80)]
153 MOV r6, r6, LSR #1
155 MOVS r0, r0, LSR #1 @ r0 = lok>>1 C = bottom bit
180 MOVS r0, r0, LSR #1 @ r0 = lok>>1 C = bottom bit
200 ADC r12,r8, r14,LSR #15 @ r12= 1+((chase+bit)<<1)+(!bit || t[chase]0x0x8000)
201 ADC r12,r12,r14,LSR #15 @ r12= t + (1+chase+bit+(!bit || t[chase]0x0x8000))<<1
213 MOVS r0, r0, LSR #1 @ r0 = lok>>1 C = bottom bit
298 MOV r8, r8, LSR r2 @ r8 = entry>>s->q_bit
[all...] |
| /external/valgrind/main/coregrind/m_dispatch/ |
| dispatch-arm-linux.S | 102 and r2, r1, r0, LSR #2 // r2 = entry #
147 and r2, r1, r0, LSR #2 // r2 = entry #
|
| /frameworks/base/media/libstagefright/codecs/on2/h264dec/source/arm_neon_asm/ |
| h264bsdFlushBits.s | 69 ADD pStrmCurrPos, pStrmBuffStart, readBits, LSR #3
|
| /frameworks/base/media/libstagefright/codecs/on2/h264dec/source/arm_neon_asm_gcc/ |
| h264bsdFlushBits.S | 67 ADD pStrmCurrPos, pStrmBuffStart, readBits, LSR #3
|
| /frameworks/base/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src/ |
| armVCM4P10_DecodeCoeffsToPair_s.s | 124 MOVS TotalCoeff, Symbol, LSR #2
191 MOVS T1, Symbol, LSR #1
299 MOV T2, T2, LSR #8
|
| /frameworks/base/media/libstagefright/codecs/on2/h264dec/source/arm11_asm/ |
| h264bsd_interpolate_hor_ver_quarter.s | 149 ADD tmp6, tmpa, tmp6, LSR #1
260 SBC mb, mb, tmp6, LSR #20 ;// -(partWidth-1)-1
261 SBC ref, ref, tmp6, LSR #20 ;// -(partWidth-1)-1
340 AND res, res, tmpb, LSR #5 ;// mask and divide by 32
391 AND res, res, tmpb, LSR #5 ;// mask and divide by 32
440 AND res, res, tmpb, LSR #5 ;// mask and divide by 32
490 AND res, res, tmpb, LSR #5 ;// mask and divide by 32
527 SBC ref, ref, tmp6, LSR #20 ;// -(partWidth-1)-1
528 SBC mb, mb, tmp6, LSR #20 ;// -(partWidth-1)-1
|
| h264bsd_interpolate_ver_half.s | 175 AND res, res, tmpb, LSR #5 ;// mask and divide by 32
219 AND res, res, tmpb, LSR #5 ;// mask and divide by 32
263 AND res, res, tmpb, LSR #5 ;// mask and divide by 32
311 AND res, res, tmpb, LSR #5 ;// mask and divide by 32
|
| h264bsd_interpolate_ver_quarter.s | 176 AND res, res, tmpb, LSR #5 ;// mask and divide by 32
228 AND res, res, tmpb, LSR #5 ;// mask and divide by 32
277 AND res, res, tmpb, LSR #5 ;// mask and divide by 32
327 AND res, res, tmpb, LSR #5 ;// mask and divide by 32
365 ADD tmp2, tmp2, tmp1, LSR #8 ;// partWidth
|
| /external/v8/test/cctest/ |
| test-disasm-arm.cc | 136 COMPARE(rsb(r6, r7, Operand(fp, LSR, 1)),
137 "e06760ab rsb r6, r7, fp, lsr #1");
138 COMPARE(rsb(r6, r7, Operand(fp, LSR, 0), SetCC),
139 "e077602b rsbs r6, r7, fp, lsr #32");
140 COMPARE(rsb(r6, r7, Operand(fp, LSR, 31), LeaveCC, pl),
141 "50676fab rsbpl r6, r7, fp, lsr #31");
201 COMPARE(cmp(r7, Operand(r8, LSR, 3), gt),
202 "c15701a8 cmpgt r7, r8, lsr #3");
|
