| /external/llvm/lib/CodeGen/ |
| LiveRangeEdit.cpp | 36 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
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| MachineSSAUpdater.cpp | 57 VRC = MRI->getRegClass(VR);
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| PHIElimination.cpp | 224 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
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| ProcessImplicitDefs.cpp | 270 const TargetRegisterClass* RC = MRI->getRegClass(Reg);
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| RegAllocFast.cpp | 266 const TargetRegisterClass *RC = MRI->getRegClass(LRI->first);
485 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
586 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
[all...] |
| RegAllocPBQP.cpp | 221 const TargetRegisterClass *trc = mri->getRegClass(vreg);
499 const TargetRegisterClass *RC = mri->getRegClass(spilled->reg);
586 const TargetRegisterClass *liRC = mri->getRegClass(li->reg);
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| MachineVerifier.cpp | 727 if (const TargetRegisterClass *DRC = TII->getRegClass(MCID,MONum,TRI)) {
736 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
747 if (const TargetRegisterClass *DRC = TII->getRegClass(MCID,MONum,TRI)) {
[all...] |
| AggressiveAntiDepBreaker.cpp | 407 RC = TII->getRegClass(MI->getDesc(), i, TRI);
482 RC = TII->getRegClass(MI->getDesc(), i, TRI);
[all...] |
| StackSlotColoring.cpp | 524 const TargetRegisterClass *RC = TII->getRegClass(MCID, i, TRI);
586 const TargetRegisterClass *RC = TII->getRegClass(MCID, i, TRI);
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| StrongPHIElimination.cpp | 691 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);
763 const TargetRegisterClass *RC = MRI->getRegClass(DestReg);
[all...] |
| TailDuplication.cpp | 385 const TargetRegisterClass *RC = MRI->getRegClass(DefReg);
422 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
[all...] |
| MachineCSE.cpp | 135 if (!MRI->constrainRegClass(SrcReg, MRI->getRegClass(Reg)))
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| MachineFunction.cpp | 395 assert(MRI.getRegClass(VReg) == RC && "Register class mismatch!");
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| MachineInstr.cpp | [all...] |
| PrologEpilogInserter.cpp | 837 const TargetRegisterClass *RC = Fn.getRegInfo().getRegClass(Reg);
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| RenderMachineFunction.cpp | 416 const TargetRegisterClass *regTRC = mri->getRegClass(reg);
[all...] |
| Splitter.cpp | 99 const TargetRegisterClass *trc = ls.mri->getRegClass(li.reg);
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| /external/llvm/lib/Target/ARM/ |
| MLxExpansionPass.cpp | 223 unsigned TmpReg = MRI->createVirtualRegister(TII->getRegClass(MCID1, 0, TRI));
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| ARMBaseRegisterInfo.cpp | [all...] |
| /external/llvm/lib/Target/PTX/ |
| PTXInstrInfo.cpp | 160 if (!MO.isReg() || RI.getRegClass(MO.getReg()) != &PTX::RegPredRegClass)
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| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
| X86RegisterInfo.cpp | 824 if (RI.getRegClass(Reg)->getAlignment() > StackAlignment) {
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| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.cpp | 407 CodeGenRegisterClass *CodeGenRegBank::getRegClass(Record *Def) {
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGRRList.cpp | 298 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
306 const TargetRegisterClass *RC = TII->getRegClass(Desc, Idx, TRI);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 177 if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) {
[all...] |
