| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 376 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem : local
380 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue,
497 unsigned opc = N->getOpcode(); local
499 switch (opc) {
567 bool isFPCmp, unsigned Opc) {
606 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
608 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg())
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | 300 unsigned opc; // target opcode member in struct:llvm::TargetLowering::IntrinsicInfo
[all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassemblerCore.cpp | 682 // MCRR, MCRR2, MRRC, MRRc2: cop opc Rd Rn CRm
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.cpp | [all...] |
