| /external/qemu/ |
| cache-utils.c | 47 unsigned cacheline; local
50 len = sizeof(cacheline);
51 if (sysctl(name, 2, &cacheline, &len, NULL, 0)) {
54 qemu_cache_conf.dcache_bsize = cacheline;
55 qemu_cache_conf.icache_bsize = cacheline;
71 unsigned cacheline; local
73 if (sysctlbyname ("machdep.cacheline_size", &cacheline, &len, NULL, 0)) {
79 qemu_cache_conf.dcache_bsize = cacheline;
80 qemu_cache_conf.icache_bsize = cacheline;
|
| /external/kernel-headers/original/asm-x86/ |
| cache.h | 11 /* vSMP Internode cacheline shift */
|
| segment_32.h | 12 * 4 - unused <==== new cacheline
26 * 12 - kernel code segment <==== new cacheline
|
| processor_32.h | 336 * pads the TSS to be cacheline-aligned (size is 0x100)
|
| /external/kernel-headers/original/linux/ |
| cache.h | 47 * These could be inter-node cacheline sizes/L3 cacheline
|
| blkdev.h | 126 * try to put the fields that are referenced together in the same cacheline
319 * Together with queue_head for cacheline sharing
|
| mmzone.h | 258 * give them a chance of being in the same cacheline.
283 * Right now a zonelist takes up less than a cacheline. We never
|
| skbuff.h | 991 * perhaps setting it to a cacheline in size (since that will maintain
992 * cacheline alignment of the DMA). It must be a power of 2.
[all...] |
| /external/valgrind/tsan/ |
| thread_sanitizer.cc | [all...] |
| /external/oprofile/events/arm/armv6/ |
| events | 14 event:0x0c counters:0,1 um:zero minimum:500 name:DCACHE_WB : data cache writeback, 1 event for every half cacheline
|
| /external/oprofile/events/arm/xscale1/ |
| events | 15 event:0x0c counters:1,2 um:zero minimum:500 name:DCACHE_WB : data cache writeback, 1 event for every half cacheline
|
| /external/oprofile/events/arm/xscale2/ |
| events | 15 event:0x0c counters:1,2,3,4 um:zero minimum:500 name:DCACHE_WB : data cache writeback, 1 event for every half cacheline
|
| /external/valgrind/main/helgrind/ |
| libhb_core.c | 86 # define CHECK_ZSM 1 /* do sanity-check CacheLine stuff */
90 # define CHECK_ZSM 0 /* don't sanity-check CacheLine stuff */
169 /* ------ CacheLine ------ */
180 CacheLine;
220 CacheLine-sized chunks of SecMaps are copied into a Cache, being
276 /* Each tag is the address of the associated CacheLine, rounded down
277 to a CacheLine address boundary. A CacheLine size must be a power
285 CacheLine lyns0[N_WAY_NENT];
292 a CacheLine. *
[all...] |
| /external/kernel-headers/original/asm-generic/bitops/ |
| atomic.h | 15 * Since "a" is usually an address, use one spinlock per cacheline.
|
| /external/kernel-headers/original/linux/netfilter_ipv4/ |
| ip_conntrack.h | 127 /* Traversed often, so hopefully in different cacheline to top */
|
| /external/webp/src/dec/ |
| vp8i.h | 90 // With this layout, BPS (=Bytes Per Scan-line) is one cacheline size.
|
| /prebuilt/linux-x86/toolchain/i686-linux-glibc2.7-4.4.3/sysroot/usr/include/asm/ |
| unistd_64.h | 14 /* at least 8 syscall per cacheline */
|
| /external/oprofile/opcontrol/ |
| opcontrol.cpp | 169 "data cache writeback, 1 event for every half cacheline"},
|
| /external/oprofile/events/ppc64/power6/ |
| events | [all...] |
| /external/llvm/lib/Target/X86/ |
| README.txt | 440 Make sure the instruction which starts a loop does not cross a cacheline
444 In the new trace, the hot loop has an instruction which crosses a cacheline
447 to grab the bytes from the next cacheline.
[all...] |
| /external/oprofile/events/i386/nehalem/ |
| unit_masks | 184 0x02 l1d Counts the number of cycles that cacheline in the L1 data cache unit is locked
|
| /external/oprofile/events/ppc64/power7/ |
| events | [all...] |
| /external/valgrind/main/callgrind/ |
| sim.c | 73 Bool sectored; /* prefetch nearside cacheline on read */
[all...] |
| /external/valgrind/main/drd/tests/ |
| tsan_unittest.cpp | [all...] |
| /external/valgrind/unittest/ |
| racecheck_unittest.cc | [all...] |
