| /external/llvm/test/CodeGen/Mips/ |
| o32_cc.ll | 18 ; CHECK: lwc1 $f12, %lo
19 ; CHECK: lwc1 $f14, %lo
29 ; CHECK: lwc1 $f12, %lo
41 ; CHECK: lwc1 $f14, %lo
89 ; CHECK: lwc1 $f12, %lo
153 ; CHECK: lwc1 $f12, %lo
154 ; CHECK: lwc1 $f14, %lo
166 ; CHECK: lwc1 $f12, %lo
181 ; CHECK: lwc1 $f14, %lo
192 ; CHECK: lwc1 $f12, %l
[all...] |
| 2009-11-16-CstPoolLoad.ll | 8 ; CHECK: lwc1 $f0, %lo($CPI0_0)($2)
|
| /external/webkit/Source/JavaScriptCore/assembler/ |
| MacroAssemblerMIPS.h | [all...] |
| MIPSAssembler.h | 539 void lwc1(FPRegisterID ft, RegisterID rs, int offset) function in class:JSC::MIPSAssembler
|
| /external/llvm/lib/Target/Mips/ |
| MipsISelDAGToDAG.cpp | 165 // lwc1 $f0, 0($2)
168 // lwc1 $f0, %lo($CPI1_0)($2)
232 SDNode *LD0 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32,
239 SDNode *LD1 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32,
|
| MipsInstrInfo.cpp | 50 if ((MI->getOpcode() == Mips::LW) || (MI->getOpcode() == Mips::LWC1) ||
209 BuildMI(MBB, I, DL, get(Mips::LWC1), DestReg).addFrameIndex(FI).addImm(0);
217 BuildMI(MBB, I, DL, get(Mips::LWC1), SubSet[0])
219 BuildMI(MBB, I, DL, get(Mips::LWC1), SubSet[1])
|
| MipsInstrFPU.td | 201 // LWC1 and SWC1 can always be emitted with odd registers.
202 def LWC1 : FFI<0b110001, (outs FGR32:$ft), (ins mem:$addr), "lwc1\t$ft, $addr",
|
| /external/v8/src/mips/ |
| constants-mips.cc | 334 case LWC1:
|
| disasm-mips.cc | 878 case LWC1:
879 Format(instr, "lwc1 'ft, 'imm16s('rs)");
|
| assembler-mips.cc | 1586 void Assembler::lwc1(FPURegister fd, const MemOperand& src) { function in class:v8::internal::Assembler
[all...] |
| constants-mips.h | 240 LWC1 = ((6 << 3) + 1) << kOpcodeShift,
|
| assembler-mips.h | 672 void lwc1(FPURegister fd, const MemOperand& src);
[all...] |
| simulator-mips.cc | [all...] |
| macro-assembler-mips.cc | 857 lwc1(double_scratch, FieldMemOperand(source, HeapNumber::kMantissaOffset));
[all...] |
| /external/webkit/Source/JavaScriptCore/ |
| ChangeLog-2010-05-24 | [all...] |
