| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineShifts.cpp | 517 BinaryOperator *ShiftOp = dyn_cast<BinaryOperator>(Op0);
518 if (ShiftOp && !ShiftOp->isShift())
519 ShiftOp = 0;
521 if (ShiftOp && isa<ConstantInt>(ShiftOp->getOperand(1))) {
522 ConstantInt *ShiftAmt1C = cast<ConstantInt>(ShiftOp->getOperand(1));
527 Value *X = ShiftOp->getOperand(0);
534 if (I.getOpcode() == ShiftOp->getOpcode()) {
550 ShiftOp->getOpcode() != Instruction::Shl)
[all...] |
| /external/qemu/target-arm/ |
| neon_helper.c | 469 uint64_t HELPER(neon_shl_u64)(uint64_t val, uint64_t shiftop)
471 int8_t shift = (int8_t)shiftop;
499 uint64_t HELPER(neon_shl_s64)(uint64_t valop, uint64_t shiftop)
501 int8_t shift = (int8_t)shiftop;
532 uint32_t HELPER(neon_rshl_s32)(uint32_t valop, uint32_t shiftop)
536 int8_t shift = (int8_t)shiftop;
550 uint64_t HELPER(neon_rshl_s64)(uint64_t valop, uint64_t shiftop)
552 int8_t shift = (int8_t)shiftop;
592 uint32_t HELPER(neon_rshl_u32)(uint32_t val, uint32_t shiftop)
595 int8_t shift = (int8_t)shiftop;
[all...] |
| translate.c | 445 static inline void gen_arm_shift_im(TCGv var, int shiftop, int shift, int flags)
447 switch (shiftop) {
494 static inline void gen_arm_shift_reg(TCGv var, int shiftop,
498 switch (shiftop) {
505 switch (shiftop) {
855 int val, rm, shift, shiftop; local
869 shiftop = (insn >> 5) & 3;
871 gen_arm_shift_im(offset, shiftop, shift, 0);
6850 int set_cc, logic_cc, shiftop; local
7789 int shiftop; local
[all...] |
| /external/v8/src/arm/ |
| constants-arm.h | 287 enum ShiftOp {
294 // Use a special code to make the distinction. The RRX ShiftOp is only used
644 inline int ShiftValue() const { return static_cast<ShiftOp>(Bits(6, 5)); }
645 inline ShiftOp ShiftField() const {
646 return static_cast<ShiftOp>(BitField(6, 5));
|
| assembler-arm.h | 387 explicit Operand(Register rm, ShiftOp shift_op, int shift_imm);
390 explicit Operand(Register rm, ShiftOp shift_op, Register rs);
410 ShiftOp shift_op() const { return shift_op_; }
415 ShiftOp shift_op_;
443 ShiftOp shift_op, int shift_imm, AddrMode am = Offset);
466 ShiftOp shift_op_;
[all...] |
| assembler-arm.cc | 168 Operand::Operand(Register rm, ShiftOp shift_op, int shift_imm) {
184 Operand::Operand(Register rm, ShiftOp shift_op, Register rs) {
210 ShiftOp shift_op, int shift_imm, AddrMode am) {
[all...] |
| disasm-arm.cc | 211 ShiftOp shift = instr->ShiftField();
[all...] |
| simulator-arm.cc | [all...] |
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 427 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
428 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
441 O << ARM_AM::getSORegOffset(ShiftOp);
|
| /external/webkit/Source/JavaScriptCore/dfg/ |
| DFGNonSpeculativeJIT.cpp | 255 shiftOp(op, op1.registerID(), shiftAmount, result.registerID());
266 shiftOp(op, reg1, reg2, result.registerID());
|
| DFGSpeculativeJIT.cpp | 305 shiftOp(op, op1.registerID(), valueOfInt32Constant(node.child2) & 0x1f, result.registerID());
316 shiftOp(op, reg1, reg2, result.registerID());
|
| DFGJITCodeGenerator.h | 340 void shiftOp(NodeType op, MacroAssembler::RegisterID op1, int32_t shiftAmount, MacroAssembler::RegisterID result)
356 void shiftOp(NodeType op, MacroAssembler::RegisterID op1, MacroAssembler::RegisterID shiftAmount, MacroAssembler::RegisterID result)
[all...] |
| /dalvik/vm/compiler/codegen/arm/ |
| CodegenDriver.cpp | 777 bool shiftOp = false;
829 shiftOp = true;
834 shiftOp = true;
839 shiftOp = true;
855 if (shiftOp) {
[all...] |
| /external/doclava/src/com/google/doclava/parser/ |
| Java.g | 1034 (shiftOp additiveExpression
1039 shiftOp
[all...] |
| JavaParser.java | 374 "synpred229_Java", "synpred170_Java", "shiftOp", "synpred134_Java",
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMCodeEmitter.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.cpp | [all...] |
