| /external/llvm/lib/Target/SystemZ/ |
| SystemZRegisterInfo.td | 17 class SystemZRegWithSubregs<string n, list<Register> subregs>
18 : RegisterWithSubRegs<n, subregs> {
30 class GPR64<bits<4> num, string n, list<Register> subregs,
32 : SystemZRegWithSubregs<n, subregs> {
38 class GPR128<bits<4> num, string n, list<Register> subregs,
40 : SystemZRegWithSubregs<n, subregs> {
51 class FPRL<bits<4> num, string n, list<Register> subregs>
52 : SystemZRegWithSubregs<n, subregs> {
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| /external/llvm/lib/CodeGen/ |
| LiveVariables.cpp | 193 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
194 unsigned SubReg = *SubRegs; ++SubRegs) {
217 for (const unsigned *SubRegs = TRI->getSubRegisters(DefReg);
218 unsigned SubReg = *SubRegs; ++SubRegs)
248 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
249 unsigned SubReg = *SubRegs; ++SubRegs) {
273 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg)
[all...] |
| DeadMachineInstructionElim.cpp | 172 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
173 *SubRegs; ++SubRegs)
174 LivePhysRegs.reset(*SubRegs);
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| RegisterScavenging.cpp | 40 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
41 unsigned SubReg = *SubRegs; ++SubRegs)
202 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
203 unsigned SubReg = *SubRegs; ++SubRegs)
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| PostRASchedulerList.cpp | 373 // Repeat, for all subregs.
388 // Repeat, for all subregs.
454 // instruction are now dead. Mark register and all subregs as they
467 // Repeat for all subregs.
487 // A register is not killed if any subregs are live...
512 // Mark any used register (that is not using undef) and subregs as
|
| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.cpp | 51 return SubRegs;
54 std::vector<Record*> SubList = TheDef->getValueAsListOfDefs("SubRegs");
58 " SubRegIndices doesn't match SubRegs");
60 // First insert the direct subregs and make sure they are fully indexed.
63 if (!SubRegs.insert(std::make_pair(Indices[i], SR)).second)
68 // Keep track of inherited subregs and how they can be reached.
71 // Clone inherited subregs and place duplicate entries on Orphans.
72 // Here the order is important - earlier subregs take precedence.
84 if (!SubRegs.insert(*SI).second)
123 SubRegs[BaseIdxInit->getDef()] = R2
[all...] |
| CodeGenRegisters.h | 52 return SubRegs;
81 SubRegMap SubRegs;
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| /external/llvm/lib/Target/ARM/ |
| ARMRegisterInfo.td | 15 class ARMReg<bits<4> num, string n, list<Register> subregs = []> : Register<n> {
18 let SubRegs = subregs;
266 // 32-bit SPR subregs).
288 // Subset of QPR that have 32-bit SPR subregs.
295 // Subset of QPR that have DPR_8 and SPR_8 subregs.
312 // Subset of QQPR that have 32-bit SPR subregs.
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| ARMMCInstLower.cpp | 77 assert(!MO.getSubReg() && "Subregs should be eliminated!");
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| ARMExpandPseudoInsts.cpp | 437 // For an instruction writing double-spaced subregs, the pseudo instruction
448 // Copy the super-register source operand used for double-spaced subregs over
571 // Add the subregs as sources of the new instruction.
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCRegisterInfo.h | 28 /// alias EAX. The SubRegs field is a zero terminated array of registers that
37 const unsigned *SubRegs; // Sub-register set, described above
145 return get(RegNo).SubRegs;
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| /external/llvm/lib/Target/Sparc/ |
| SparcRegisterInfo.td | 38 class Rd<bits<5> num, string n, list<Register> subregs> : SparcReg<n> {
40 let SubRegs = subregs;
|
| /external/llvm/lib/Target/Mips/ |
| MipsRegisterInfo.td | 20 class MipsRegWithSubRegs<string n, list<Register> subregs>
21 : RegisterWithSubRegs<n, subregs> {
41 class AFPR<bits<5> num, string n, list<Register> subregs>
42 : MipsRegWithSubRegs<n, subregs> {
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| MipsFrameLowering.cpp | 220 const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
223 MachineLocation SrcML0(*SubRegs);
224 MachineLocation SrcML1(*(SubRegs + 1));
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| /external/llvm/lib/Target/MSP430/ |
| MSP430RegisterInfo.td | 19 class MSP430RegWithSubregs<bits<4> num, string n, list<Register> subregs>
20 : RegisterWithSubRegs<n, subregs> {
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| /external/llvm/include/llvm/Target/ |
| Target.td | 48 // SubRegs - A list of registers that are parts of this register. Note these
50 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
52 list<Register> SubRegs = [];
54 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
56 // SubRegs.
64 // a register in SubRegs and are not inherited. The following formats are
93 // List "subregs" specifies which registers are sub-registers to this one. This
94 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
97 class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
98 let SubRegs = subregs
[all...] |
| /external/llvm/lib/Target/Blackfin/ |
| BlackfinRegisterInfo.td | 14 // Subregs are:
44 // Ri - 32-bit integer registers with subregs
52 let SubRegs = subs;
64 // Rii - 32-bit integer registers with subregs
67 let SubRegs = subs;
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| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.td | 36 let SubRegs = [SubReg];
56 class CR<bits<3> num, string n, list<Register> subregs> : PPCReg<n> {
58 let SubRegs = subregs;
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| PPCMCInstLower.cpp | 145 assert(!MO.getSubReg() && "Subregs should be eliminated!");
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| /bionic/libc/kernel/arch-x86/asm/ |
| voyager.h | 402 struct voyager_psi_subregs subregs; member in struct:voyager_psi
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| /development/ndk/platforms/android-9/arch-x86/include/asm/ |
| voyager.h | 402 struct voyager_psi_subregs subregs; member in struct:voyager_psi
|
| /external/llvm/include/llvm/CodeGen/ |
| Passes.h | 138 /// LowerSubregs Pass - This pass lowers subregs to register-register copies
|
| /prebuilt/ndk/android-ndk-r4/platforms/android-5/arch-x86/usr/include/asm/ |
| voyager.h | 402 struct voyager_psi_subregs subregs; member in struct:voyager_psi
|
| /prebuilt/ndk/android-ndk-r4/platforms/android-8/arch-x86/usr/include/asm/ |
| voyager.h | 402 struct voyager_psi_subregs subregs; member in struct:voyager_psi
|
| /prebuilt/ndk/android-ndk-r6/platforms/android-9/arch-x86/usr/include/asm/ |
| voyager.h | 402 struct voyager_psi_subregs subregs; member in struct:voyager_psi
|
