| /external/llvm/include/llvm/CodeGen/ |
| RegAllocPBQP.h | 35 /// to a register allocation solution. (i.e. The PBQP-node <--> vreg map,
48 /// and the set of allowed pregs for the vreg.
54 void recordVReg(unsigned vreg, PBQP::Graph::NodeItr node,
57 assert(vreg2Node.find(vreg) == vreg2Node.end() && "Re-mapping vreg.");
58 assert(allowedSets[vreg].empty() && "vreg already has pregs.");
60 node2VReg[node] = vreg;
61 vreg2Node[vreg] = node;
62 std::copy(arBegin, arEnd, std::back_inserter(allowedSets[vreg]));
[all...] |
| MachineRegisterInfo.h | 25 /// registers, including vreg register classes, use/def chains for registers,
30 /// Each element in this list contains the register class of the vreg and the
266 void addLiveIn(unsigned Reg, unsigned vreg = 0) {
267 LiveIns.push_back(std::make_pair(Reg, vreg));
286 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
288 unsigned getLiveInPhysReg(unsigned VReg) const;
|
| MachineSSAUpdater.h | 32 /// vreg with uses of a set of vregs.
|
| FastISel.h | 103 /// TryToFoldLoad - The specified machine instr operand is a vreg, and that
104 /// vreg is being provided by the specified load instruction. If possible,
|
| LiveIntervalAnalysis.h | 410 unsigned vreg; member in struct:llvm::LiveIntervals::SRInfo
413 : index(i), vreg(vr), canFold(f) {}
|
| /external/valgrind/main/VEX/priv/ |
| host_generic_reg_alloc2.c | 107 vreg. Is safely left at False, and becomes True after a
113 Bound /* in use (holding value of some vreg) */
116 /* If .disp == Bound, what vreg is it bound to? */
117 HReg vreg; member in struct:__anon11826
123 (vreg_state) from vreg numbers back to entries in rreg_state. It
125 hregNumber(rreg_state[j].vreg) == i -- that is, the two entries
127 which involve looking for a particular vreg: there is no need to
129 vreg_state. The FAQ "does this vreg already have an associated
132 To indicate, in vreg_state[i], that a given vreg is not currently
165 finding the vreg which is mentioned as far ahead as possible, i
352 HReg rreg, vreg, vregS, vregD; local
[all...] |
| host_generic_regs.c | 167 vpanic("addToHRegMap: orig is not a vreg");
169 vpanic("addToHRegMap: replacement is not a vreg");
|
| /external/llvm/lib/CodeGen/ |
| RegAllocPBQP.cpp | 141 /// \brief Finds the initial set of vreg intervals to allocate.
165 assert(vregItr != node2VReg.end() && "No vreg for node.");
169 PBQP::Graph::NodeItr PBQPRAProblem::getNodeForVReg(unsigned vreg) const {
170 VReg2Node::const_iterator nodeItr = vreg2Node.find(vreg);
171 assert(nodeItr != vreg2Node.end() && "No node for vreg.");
177 PBQPRAProblem::getAllowedSet(unsigned vreg) const {
178 AllowedSetMap::const_iterator allowedSetItr = allowedSets.find(vreg);
179 assert(allowedSetItr != allowedSets.end() && "No pregs for vreg.");
184 unsigned PBQPRAProblem::getPRegForOption(unsigned vreg, unsigned option) const {
185 assert(isPRegOption(vreg, option) && "Not a preg option.")
220 unsigned vreg = *vregItr; local
528 unsigned vreg = problem.getVRegForNode(node); local
[all...] |
| LiveIntervalUnion.h | 174 Query(LiveInterval *VReg, LiveIntervalUnion *LIU):
175 LiveUnion(LIU), VirtReg(VReg), CheckedFirstInterference(false),
190 void init(unsigned UTag, LiveInterval *VReg, LiveIntervalUnion *LIU) {
191 assert(VReg && LIU && "Invalid arguments");
192 if (UserTag == UTag && VirtReg == VReg &&
199 VirtReg = VReg;
235 bool isSeenInterference(LiveInterval *VReg) const;
240 // Did collectInterferingVRegs encounter an unspillable vreg?
|
| MachineRegisterInfo.cpp | 34 "Vreg use list non-empty still?");
92 // The back pointers for the vreg lists point into the previous vector.
165 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
167 unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {
169 if (I->second == VReg)
|
| LiveIntervalAnalysis.cpp | 294 // done once for the vreg. We use an empty interval to detect the first
295 // time we see a vreg.
318 // Loop over all of the blocks that the vreg is defined in. There are
319 // two cases we have to handle here. The most common case is a vreg
401 // the result of two address elimination, then the vreg is one of the
[all...] |
| LiveRangeEdit.cpp | 36 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
38 VRM.setIsSplitFromReg(VReg, VRM.getOriginal(OldReg));
39 LiveInterval &LI = LIS.getOrCreateInterval(VReg);
|
| LiveIntervalUnion.cpp | 149 // a live vreg with thousands of segments, then change this code to use
252 // Advance the union's iterator to reach an unseen interfering vreg.
260 // Cache the most recent interfering vreg to bypass isSeenInterference.
286 // Cache the most recent interfering vreg to bypass isSeenInterference.
|
| MachineFunction.cpp | 393 unsigned VReg = MRI.getLiveInVirtReg(PReg);
394 if (VReg) {
395 assert(MRI.getRegClass(VReg) == RC && "Register class mismatch!");
396 return VReg;
398 VReg = MRI.createVirtualRegister(RC);
399 MRI.addLiveIn(PReg, VReg);
400 return VReg;
|
| PHIElimination.cpp | 66 /// vreg is coming from. This is used later to determine when the vreg
376 // This vreg no longer lives all of the way through opBlock.
389 /// used in a PHI node. We map that to the BB the vreg is coming from. This is
390 /// used later to determine when the vreg is killed in the BB.
|
| RegAllocBasic.cpp | 196 assert(!VisitedVRegs.intersects(VRegs) && "vreg in multiple unions");
200 // Verify vreg coverage.
210 llvm_unreachable("unallocated live vreg");
390 // Deallocate the interfering vreg by removing it from the union.
424 // Spill each interfering vreg allocated to PhysReg or an alias.
|
| TailDuplication.cpp | 220 unsigned VReg = SSAUpdateVRs[i];
221 SSAUpdate.Initialize(VReg);
225 MachineInstr *DefMI = MRI->getVRegDef(VReg);
229 SSAUpdate.AddAvailableValue(DefBB, VReg);
234 SSAUpdateVals.find(VReg);
242 MachineRegisterInfo::use_iterator UI = MRI->use_begin(VReg);
[all...] |
| /dalvik/vm/compiler/codegen/ |
| CodegenFactory.cpp | 176 int vReg = dvmCompilerS2VReg(cUnit, rlDest.sRegLow);
177 storeBaseDisp(cUnit, rFP, vReg << 2, rlDest.lowReg, kWord);
257 int vReg = dvmCompilerS2VReg(cUnit, rlDest.sRegLow);
258 assert((vReg+1) == dvmCompilerS2VReg(cUnit,
260 storeBaseDispWide(cUnit, rFP, vReg << 2, rlDest.lowReg,
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 75 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
76 // the CopyToReg'd destination register instead of creating a new vreg.
189 // is a vreg in the same register class, use the CopyToReg'd destination
190 // register instead of creating a new vreg.
244 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());
247 if (!VReg) {
249 VReg = MRI->createVirtualRegister(RC);
252 TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
253 return VReg;
275 unsigned VReg = getVR(Op, VRBaseMap)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb1RegisterInfo.cpp | 600 unsigned VReg = 0;
681 // register. The offset is already handled in the vreg value.
684 VReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass);
689 emitThumbRegPlusImmInReg(MBB, II, dl, VReg, FrameReg,
692 emitLoadConstPool(MBB, II, dl, VReg, 0, Offset);
696 emitThumbRegPlusImmediate(MBB, II, dl, VReg, FrameReg, Offset, TII,
699 MI.getOperand(i).ChangeToRegister(VReg, false, false, true);
702 // register. The offset is already handled in the vreg value.
|
| /system/core/libpixelflinger/codeflinger/ |
| blending.cpp | 541 int vreg = v.reg;
544 MOV(AL, 0, d.reg, reg_imm(vreg, LSR, vshift));
545 vreg = d.reg;
548 MOV(AL, 0, d.reg, reg_imm(vreg, LSR, fshift));
551 if (smulw) SMULW(AL, xy, d.reg, vreg, freg);
552 else SMUL(AL, xy, d.reg, vreg, freg);
|
| /external/llvm/include/llvm/Target/ |
| TargetOpcodes.h | 75 // the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index
|
| /external/llvm/lib/Target/ |
| TargetRegisterInfo.cpp | 38 OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg);
|
| /external/webkit/Source/JavaScriptCore/jit/ |
| JITInlineMethods.h | 264 ALWAYS_INLINE void JIT::linkSlowCaseIfNotJSCell(Vector<SlowCaseEntry>::iterator& iter, int vReg)
266 if (!m_codeBlock->isKnownNotImmediate(vReg))
742 ALWAYS_INLINE void JIT::emitJumpSlowCaseIfNotJSCell(RegisterID reg, int vReg)
744 if (!m_codeBlock->isKnownNotImmediate(vReg))
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
