Lines Matching refs:BASE
72 outw(RX_DISABLE, BASE + EP_COMMAND);
73 outw(RX_DISCARD_TOP_PACK, BASE + EP_COMMAND);
74 while (inw(BASE + EP_STATUS) & S_COMMAND_IN_PROGRESS)
76 outw(TX_DISABLE, BASE + EP_COMMAND);
77 outw(STOP_TRANSCEIVER, BASE + EP_COMMAND);
79 outw(RX_RESET, BASE + EP_COMMAND);
80 outw(TX_RESET, BASE + EP_COMMAND);
81 outw(C_INTR_LATCH, BASE + EP_COMMAND);
82 outw(SET_RD_0_MASK, BASE + EP_COMMAND);
83 outw(SET_INTR_MASK, BASE + EP_COMMAND);
84 outw(SET_RX_FILTER, BASE + EP_COMMAND);
89 while (inw(BASE + EP_STATUS) & S_COMMAND_IN_PROGRESS)
95 outw(0, BASE + EP_W0_CONFIG_CTRL);
98 outw(SET_IRQ(0), BASE + EP_W0_RESOURCE_CFG);
101 outw(ENABLE_DRQ_IRQ, BASE + EP_W0_CONFIG_CTRL);
107 outb(nic->node_addr[i], BASE + EP_W2_ADDR_0 + i);
109 outw(RX_RESET, BASE + EP_COMMAND);
110 outw(TX_RESET, BASE + EP_COMMAND);
115 inb(BASE + EP_W1_TX_STATUS);
118 outw(ACK_INTR | 0xff, BASE + EP_COMMAND);
120 outw(SET_RD_0_MASK | S_5_INTS, BASE + EP_COMMAND);
122 outw(SET_INTR_MASK, BASE + EP_COMMAND);
124 outw(SET_RX_FILTER | FIL_INDIVIDUAL | FIL_BRDCST, BASE + EP_COMMAND);
128 outw(START_TRANSCEIVER, BASE + EP_COMMAND);
134 outw(ENABLE_UTP, BASE + EP_W4_MEDIA_TYPE);
140 outw(RX_ENABLE, BASE + EP_COMMAND);
141 outw(TX_ENABLE, BASE + EP_COMMAND);
144 outw(SET_RX_EARLY_THRESH | ETH_ZLEN, BASE + EP_COMMAND);
145 outw(SET_TX_START_THRESH | 16, BASE + EP_COMMAND);
185 while ((status=inb(BASE + EP_W1_TX_STATUS)) & TXS_COMPLETE ) {
187 outw(TX_RESET, BASE + EP_COMMAND);
188 outw(TX_ENABLE, BASE + EP_COMMAND);
190 outb(0x0, BASE + EP_W1_TX_STATUS);
193 while (inw(BASE + EP_W1_FREE_TX) < (unsigned short)len + pad + 4)
196 outw(len, BASE + EP_W1_TX_PIO_WR_1);
197 outw(0x0, BASE + EP_W1_TX_PIO_WR_1); /* Second dword meaningless */
200 outsw(BASE + EP_W1_TX_PIO_WR_1, d, ETH_ALEN/2);
201 outsw(BASE + EP_W1_TX_PIO_WR_1, nic->node_addr, ETH_ALEN/2);
202 outw(t, BASE + EP_W1_TX_PIO_WR_1);
203 outsw(BASE + EP_W1_TX_PIO_WR_1, p, s / 2);
205 outb(*(p+s - 1), BASE + EP_W1_TX_PIO_WR_1);
208 outb(0, BASE + EP_W1_TX_PIO_WR_1); /* Padding */
211 while((inw(BASE + EP_STATUS) & S_COMMAND_IN_PROGRESS) != 0)
226 cst=inw(BASE + EP_STATUS);
235 outw(ACK_INTR| (cst & S_5_INTS), BASE + EP_COMMAND);
236 outw(C_INTR_LATCH, BASE + EP_COMMAND);
241 status = inw(BASE + EP_W1_RX_STATUS);
247 outw(RX_DISCARD_TOP_PACK, BASE + EP_COMMAND);
259 insw(BASE + EP_W1_RX_PIO_RD_1, nic->packet, rx_fifo / 2);
261 nic->packet[rx_fifo-1]=inb(BASE + EP_W1_RX_PIO_RD_1);
265 status = inw(BASE + EP_W1_RX_STATUS);
271 insw(BASE + EP_W1_RX_PIO_RD_1, nic->packet+nic->packetlen, rx_fifo / 2);
273 nic->packet[nic->packetlen+rx_fifo-1]=inb(BASE + EP_W1_RX_PIO_RD_1);
288 outw(RX_DISCARD_TOP_PACK, BASE + EP_COMMAND);
289 while (inw(BASE + EP_STATUS) & S_COMMAND_IN_PROGRESS)
601 outw(ntohs(p[i]), BASE + EP_W2_ADDR_0 + (i * 2));
