Lines Matching refs:N0
230 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2);
231 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2,
234 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
242 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
244 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1);
525 SDValue N0, N1, N2;
526 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
532 SDValue N0, SDValue N1) {
533 EVT VT = N0.getValueType();
534 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
539 cast<ConstantSDNode>(N0.getOperand(1)),
541 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
543 if (N0.hasOneUse()) {
545 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
546 N0.getOperand(0), N1);
548 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
553 if (isa<ConstantSDNode>(N0)) {
558 cast<ConstantSDNode>(N0));
563 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
564 N1.getOperand(0), N0);
778 SDValue N0 = Op.getOperand(0);
779 SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
786 if (N0 == N1)
799 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
836 SDValue N0 = Op.getOperand(0);
838 N0 = SExtPromoteOperand(Op.getOperand(0), PVT);
840 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT);
842 N0 = PromoteOperand(N0, PVT, Replace);
843 if (N0.getNode() == 0)
846 AddToWorkList(N0.getNode());
848 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
854 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1)));
1169 SDValue N0 = N->getOperand(0);
1173 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
1174 SDValue Ops[] = { N1, N0 };
1294 SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1,
1296 EVT VT = N0.getValueType();
1297 SDValue N00 = N0.getOperand(0);
1298 SDValue N01 = N0.getOperand(1);
1304 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT,
1309 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
1316 SDValue N0 = N->getOperand(0);
1318 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1320 EVT VT = N0.getValueType();
1329 if (N0.getOpcode() == ISD::UNDEF)
1330 N0;
1338 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0);
1341 return N0;
1343 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1350 if (N1C && N0.getOpcode() == ISD::SUB)
1351 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
1355 N0.getOperand(1));
1357 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1);
1361 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
1362 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
1363 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1));
1367 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1));
1369 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1372 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1373 return N0.getOperand(0);
1376 N0 == N1.getOperand(1).getOperand(0))
1381 N0 == N1.getOperand(1).getOperand(1))
1387 N0 == N1.getOperand(0).getOperand(1))
1392 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1393 SDValue N00 = N0.getOperand(0);
1394 SDValue N01 = N0.getOperand(1);
1400 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10),
1412 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1421 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1);
1426 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
1427 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG);
1431 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG);
1441 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0,
1445 if (N0.getOpcode() == ISD::SHL &&
1446 N0.getOperand(0).getOpcode() == ISD::SUB)
1448 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0)))
1452 N0.getOperand(0).getOperand(1),
1453 N0.getOperand(1)));
1470 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
1471 N0.getOperand(0).getValueType() == MVT::i1 &&
1474 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
1482 SDValue N0 = N->getOperand(0);
1484 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1486 EVT VT = N0.getValueType();
1490 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0),
1496 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1500 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1507 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1516 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1),
1525 SDValue N0 = N->getOperand(0);
1528 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1534 N1, N0, CarryIn);
1538 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1561 SDValue N0 = N->getOperand(0);
1563 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1567 EVT VT = N0.getValueType();
1577 if (N0 == N1)
1584 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0,
1588 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
1590 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
1593 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1594 return N0.getOperand(1);
1596 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1597 return N0.getOperand(0);
1605 if (N0.getOpcode() == ISD::ADD &&
1606 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1607 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1608 N0.getOperand(1).getOperand(0) == N1)
1609 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT,
1610 N0.getOperand(0), N0.getOperand(1).getOperand(1));
1612 if (N0.getOpcode() == ISD::ADD &&
1613 N0.getOperand(1).getOpcode() == ISD::ADD &&
1614 N0.getOperand(1).getOperand(1) == N1)
1616 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1618 if (N0.getOpcode() == ISD::SUB &&
1619 N0.getOperand(1).getOpcode() == ISD::SUB &&
1620 N0.getOperand(1).getOperand(1) == N1)
1622 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1625 if (N0.getOpcode() == ISD::UNDEF)
1626 return N0;
1631 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1649 SDValue N0 = N->getOperand(0);
1651 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1653 EVT VT = N0.getValueType();
1662 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1669 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0);
1676 DAG.getConstant(0, VT), N0);
1679 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1681 getShiftAmountTy(N0.getValueType())));
1689 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1691 getShiftAmountTy(N0.getValueType()))));
1694 if (N1C && N0.getOpcode() == ISD::SHL &&
1695 isa<ConstantSDNode>(N0.getOperand(1))) {
1697 N1, N0.getOperand(1));
1700 N0.getOperand(0), C3);
1708 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1709 N0.getNode()->hasOneUse()) {
1710 Sh = N0; Y = N1;
1714 Sh = N1; Y = N0;
1726 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
1727 isa<ConstantSDNode>(N0.getOperand(1)))
1729 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT,
1730 N0.getOperand(0), N1),
1732 N0.getOperand(1), N1));
1735 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1);
1743 SDValue N0 = N->getOperand(0);
1745 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1760 return N0;
1764 DAG.getConstant(0, VT), N0);
1768 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1770 N0, N1);
1786 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
1788 getShiftAmountTy(N0.getValueType())));
1791 // Add (N0 < 0) ? abs2 - 1 : 0;
1795 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL);
1820 if (N0.getOpcode() == ISD::UNDEF)
1830 SDValue N0 = N->getOperand(0);
1832 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1847 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
1849 getShiftAmountTy(N0.getValueType())));
1861 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add);
1872 if (N0.getOpcode() == ISD::UNDEF)
1882 SDValue N0 = N->getOperand(0);
1884 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1894 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1895 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1);
1901 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1);
1907 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1914 if (N0.getOpcode() == ISD::UNDEF)
1924 SDValue N0 = N->getOperand(0);
1926 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1935 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0,
1946 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add);
1954 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1);
1960 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1967 if (N0.getOpcode() == ISD::UNDEF)
1977 SDValue N0 = N->getOperand(0);
1988 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0,
1989 DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
1990 getShiftAmountTy(N0.getValueType())));
1992 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2002 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
2004 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2015 SDValue N0 = N->getOperand(0);
2026 return DAG.getConstant(0, N0.getValueType());
2028 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2038 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
2040 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2127 // Compute the low part as N0.
2157 // Compute the low part as N0.
2203 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2204 EVT VT = N0.getValueType();
2205 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
2208 if (N0.getNode()->getNumOperands() == 0) return SDValue();
2218 EVT Op0VT = N0.getOperand(0).getValueType();
2219 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
2220 N0.getOpcode() == ISD::SIGN_EXTEND ||
2222 (N0.getOpcode() == ISD::ANY_EXTEND &&
2224 (N0.getOpcode() == ISD::TRUNCATE &&
2231 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2232 N0.getOperand(0).getValueType(),
2233 N0.getOperand(0), N1.getOperand(0));
2235 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode);
2242 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2243 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
2244 N0.getOperand(1) == N1.getOperand(1)) {
2245 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2246 N0.getOperand(0).getValueType(),
2247 N0.getOperand(0), N1.getOperand(0));
2249 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
2250 ORNode, N0.getOperand(1));
2257 SDValue N0 = N->getOperand(0);
2260 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2272 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2279 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0);
2282 return N0;
2288 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1);
2292 if (N1C && N0.getOpcode() == ISD::OR)
2293 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2297 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2298 SDValue N0Op0 = N0.getOperand(0);
2303 N0.getValueType(), N0Op0);
2311 CombineTo(N0.getNode(), Zext);
2316 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2324 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2331 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(),
2338 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2354 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2360 if (N0.getOpcode() == N1.getOpcode()) {
2372 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
2373 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2382 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
2388 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2393 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
2394 N0.hasOneUse()) {
2395 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2404 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
2411 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2419 if (N1C && (N0.getOpcode() == ISD::LOAD ||
2420 (N0.getOpcode() == ISD::ANY_EXTEND &&
2421 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
2422 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
2424 ? cast<LoadSDNode>(N0.getOperand(0))
2425 : cast<LoadSDNode>(N0);
2427 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) {
2492 SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
2506 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
2507 std::swap(N0, N1);
2509 std::swap(N0, N1);
2510 if (N0.getOpcode() == ISD::AND) {
2511 if (!N0.getNode()->hasOneUse())
2513 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2516 N0 = N0.getOperand(0);
2530 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
2531 std::swap(N0, N1);
2532 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
2534 if (!N0.getNode()->hasOneUse() ||
2538 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2546 SDValue N00 = N0->getOperand(0);
2612 SDValue N0 = N.getOperand(0);
2617 if (N0.getOpcode() != ISD::SRL)
2619 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2625 if (N0.getOpcode() != ISD::SHL)
2627 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2652 Parts[Num] = N0.getOperand(0).getNode();
2659 SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) {
2673 if (N0.getOpcode() != ISD::OR)
2675 SDValue N00 = N0.getOperand(0);
2676 SDValue N01 = N0.getOperand(1);
2729 SDValue N0 = N->getOperand(0);
2732 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2744 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) {
2753 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0);
2756 return N0;
2761 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
2765 SDValue BSwap = MatchBSwapHWord(N, N0, N1);
2768 BSwap = MatchBSwapHWordLow(N, N0, N1);
2773 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1);
2778 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
2779 isa<ConstantSDNode>(N0.getOperand(1))) {
2780 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
2783 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
2784 N0.getOperand(0), N1),
2788 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2823 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2829 if (N0.getOpcode() == N1.getOpcode()) {
2835 if (N0.getOpcode() == ISD::AND &&
2837 N0.getOperand(1).getOpcode() == ISD::Constant &&
2840 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
2844 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
2848 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
2850 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
2851 N0.getOperand(0), N1.getOperand(0));
2858 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc()))
3049 SDValue N0 = N->getOperand(0);
3052 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3054 EVT VT = N0.getValueType();
3063 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
3066 if (N0.getOpcode() == ISD::UNDEF)
3067 return N0;
3075 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
3078 return N0;
3080 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1);
3085 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
3091 switch (N0.getOpcode()) {
3097 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2),
3098 N0.getOperand(3), NotCC);
3104 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
3105 N0.getNode()->hasOneUse() &&
3106 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
3107 SDValue V = N0.getOperand(0);
3108 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V,
3116 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3117 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3119 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3128 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3129 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3131 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3139 if (N1C && N0.getOpcode() == ISD::XOR) {
3140 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
3141 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3143 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1),
3147 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0),
3152 if (N0 == N1)
3156 if (N0.getOpcode() == N1.getOpcode()) {
3240 SDValue N0 = N->getOperand(0);
3242 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3244 EVT VT = N0.getValueType();
3252 return N0;
3258 return N0;
3260 if (N0.getOpcode() == ISD::UNDEF)
3276 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
3289 if (N1C && N0.getOpcode() == ISD::SHL &&
3290 N0.getOperand(1).getOpcode() == ISD::Constant) {
3291 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3295 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
3304 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND ||
3305 N0.getOpcode() == ISD::ANY_EXTEND ||
3306 N0.getOpcode() == ISD::SIGN_EXTEND) &&
3307 N0.getOperand(0).getOpcode() == ISD::SHL &&
3308 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
3310 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
3312 EVT InnerShiftVT = N0.getOperand(0).getValueType();
3317 return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT,
3318 DAG.getNode(N0.getOpcode(), N0->getDebugLoc(), VT,
3319 N0.getOperand(0)->getOperand(0)),
3326 if (N1C && N0.getOpcode() == ISD::SRL &&
3327 N0.getOperand(1).getOpcode() == ISD::Constant) {
3328 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3336 Shift = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
3340 Shift = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3343 return DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, Shift,
3348 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) {
3354 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
3368 SDValue N0 = N->getOperand(0);
3370 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3372 EVT VT = N0.getValueType();
3380 return N0;
3383 return N0;
3389 return N0;
3392 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
3401 N0.getOperand(0), DAG.getValueType(ExtVT));
3405 if (N1C && N0.getOpcode() == ISD::SRA) {
3406 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3409 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0),
3419 if (N0.getOpcode() == ISD::SHL) {
3421 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3440 getShiftAmountTy(N0.getOperand(0).getValueType()));
3441 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT,
3442 N0.getOperand(0), Amt);
3443 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT,
3461 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
3473 if (N0.getOpcode() == ISD::TRUNCATE &&
3474 (N0.getOperand(0).getOpcode() == ISD::SRL ||
3475 N0.getOperand(0).getOpcode() == ISD::SRA) &&
3476 N0.getOperand(0).hasOneUse() &&
3477 N0.getOperand(0).getOperand(1).hasOneUse() &&
3478 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) {
3479 EVT LargeVT = N0.getOperand(0).getValueType();
3481 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1));
3487 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType()));
3489 N0.getOperand(0).getOperand(0), Amt);
3500 if (DAG.SignBitIsZero(N0))
3501 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1);
3513 SDValue N0 = N->getOperand(0);
3515 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3517 EVT VT = N0.getValueType();
3525 return N0;
3531 return N0;
3538 if (N1C && N0.getOpcode() == ISD::SRL &&
3539 N0.getOperand(1).getOpcode() == ISD::Constant) {
3540 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3544 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3549 if (N1C && N0.getOpcode() == ISD::TRUNCATE &&
3550 N0.getOperand(0).getOpcode() == ISD::SRL &&
3551 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
3553 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
3555 EVT InnerShiftVT = N0.getOperand(0).getValueType();
3556 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType();
3562 return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT,
3563 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT,
3564 N0.getOperand(0)->getOperand(0),
3570 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 &&
3571 N0.getValueSizeInBits() <= 64) {
3572 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits();
3573 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
3579 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
3581 EVT SmallVT = N0.getOperand(0).getValueType();
3587 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT,
3588 N0.getOperand(0),
3598 if (N0.getOpcode() == ISD::SRA)
3599 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1);
3603 if (N1C && N0.getOpcode() == ISD::CTLZ &&
3607 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
3625 SDValue Op = N0.getOperand(0);
3628 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op,
3648 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
3707 SDValue N0 = N->getOperand(0);
3711 if (isa<ConstantSDNode>(N0))
3712 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0);
3717 SDValue N0 = N->getOperand(0);
3721 if (isa<ConstantSDNode>(N0))
3722 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0);
3727 SDValue N0 = N->getOperand(0);
3731 if (isa<ConstantSDNode>(N0))
3732 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0);
3737 SDValue N0 = N->getOperand(0);
3740 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3744 EVT VT0 = N0.getValueType();
3757 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
3767 N0, DAG.getConstant(1, VT0));
3768 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0,
3769 N0, DAG.getConstant(1, VT0));
3777 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
3783 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
3789 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
3792 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
3793 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
3796 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
3797 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
3804 if (N0.getOpcode() == ISD::SETCC) {
3812 N0.getOperand(0), N0.getOperand(1),
3813 N1, N2, N0.getOperand(2));
3814 return SimplifySelect(N->getDebugLoc(), N0, N1, N2);
3821 SDValue N0 = N->getOperand(0);
3833 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
3834 N0, N1, CC, N->getDebugLoc(), false);
3855 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC);
3868 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
3873 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
3874 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
3875 UE = N0.getNode()->use_end();
3880 if (UI.getUse().getResNo() != N0.getResNo())
3891 if (UseOp == N0)
3951 SDValue N0 = N->getOperand(0);
3955 if (isa<ConstantSDNode>(N0))
3956 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0);
3960 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
3962 N0.getOperand(0));
3964 if (N0.getOpcode() == ISD::TRUNCATE) {
3967 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3969 SDNode* oye = N0.getNode()->getOperand(0).getNode();
3970 if (NarrowLoad.getNode() != N0.getNode()) {
3971 CombineTo(N0.getNode(), NarrowLoad);
3980 SDValue Op = N0.getOperand(0);
3982 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits();
4005 N0.getValueType())) {
4007 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op);
4009 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op);
4011 DAG.getValueType(N0.getValueType()));
4019 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4020 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4021 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
4024 if (!N0.hasOneUse())
4025 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
4027 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4031 N0.getValueType(),
4035 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4036 N0.getValueType(), ExtLoad);
4037 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4046 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
4047 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
4048 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4059 CombineTo(N0.getNode(),
4060 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4061 N0.getValueType(), ExtLoad),
4069 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
4070 N0.getOpcode() == ISD::XOR) &&
4071 isa<LoadSDNode>(N0.getOperand(0)) &&
4072 N0.getOperand(1).getOpcode() == ISD::Constant &&
4073 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) &&
4074 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
4075 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
4079 if (!N0.hasOneUse())
4080 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND,
4090 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4092 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4095 N0.getOperand(0).getDebugLoc(),
4096 N0.getOperand(0).getValueType(), ExtLoad);
4098 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
4106 if (N0.getOpcode() == ISD::SETCC) {
4110 EVT N0VT = N0.getOperand(0).getValueType();
4117 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4118 N0.getOperand(1),
4119 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4131 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4132 N0.getOperand(1),
4133 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4143 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4145 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4152 N0.getOperand(0), N0.getOperand(1),
4153 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
4159 DAG.SignBitIsZero(N0))
4160 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
4166 SDValue N0 = N->getOperand(0);
4170 if (isa<ConstantSDNode>(N0))
4171 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
4174 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
4176 N0.getOperand(0));
4180 if (N0.getOpcode() == ISD::TRUNCATE) {
4181 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4183 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4184 if (NarrowLoad.getNode() != N0.getNode()) {
4185 CombineTo(N0.getNode(), NarrowLoad);
4194 if (N0.getOpcode() == ISD::TRUNCATE &&
4199 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4201 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4202 if (NarrowLoad.getNode() != N0.getNode()) {
4203 CombineTo(N0.getNode(), NarrowLoad);
4210 SDValue Op = N0.getOperand(0);
4217 N0.getValueType().getScalarType());
4222 if (N0.getOpcode() == ISD::AND &&
4223 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
4224 N0.getOperand(1).getOpcode() == ISD::Constant &&
4225 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
4226 N0.getValueType()) ||
4227 !TLI.isZExtFree(N0.getValueType(), VT))) {
4228 SDValue X = N0.getOperand(0).getOperand(0);
4234 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4244 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4245 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4246 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
4249 if (!N0.hasOneUse())
4250 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
4252 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4256 N0.getValueType(),
4260 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4261 N0.getValueType(), ExtLoad);
4262 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4272 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
4273 N0.getOpcode() == ISD::XOR) &&
4274 isa<LoadSDNode>(N0.getOperand(0)) &&
4275 N0.getOperand(1).getOpcode() == ISD::Constant &&
4276 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) &&
4277 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
4278 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
4282 if (!N0.hasOneUse())
4283 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND,
4293 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4295 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4298 N0.getOperand(0).getDebugLoc(),
4299 N0.getOperand(0).getValueType(), ExtLoad);
4301 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
4311 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
4312 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
4313 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4324 CombineTo(N0.getNode(),
4325 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(),
4332 if (N0.getOpcode() == ISD::SETCC) {
4336 EVT N0VT = N0.getOperand(0).getValueType();
4347 DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4348 N0.getOperand(1),
4349 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
4363 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4364 N0.getOperand(1),
4365 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4374 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4376 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4381 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
4382 isa<ConstantSDNode>(N0.getOperand(1)) &&
4383 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
4384 N0.hasOneUse()) {
4385 SDValue ShAmt = N0.getOperand(1);
4387 if (N0.getOpcode() == ISD::SHL) {
4388 SDValue InnerZExt = N0.getOperand(0);
4403 return DAG.getNode(N0.getOpcode(), DL, VT,
4404 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)),
4412 SDValue N0 = N->getOperand(0);
4416 if (isa<ConstantSDNode>(N0))
4417 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0);
4421 if (N0.getOpcode() == ISD::ANY_EXTEND ||
4422 N0.getOpcode() == ISD::ZERO_EXTEND ||
4423 N0.getOpcode() == ISD::SIGN_EXTEND)
4424 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0));
4428 if (N0.getOpcode() == ISD::TRUNCATE) {
4429 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4431 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4432 if (NarrowLoad.getNode() != N0.getNode()) {
4433 CombineTo(N0.getNode(), NarrowLoad);
4442 if (N0.getOpcode() == ISD::TRUNCATE) {
4443 SDValue TruncOp = N0.getOperand(0);
4453 if (N0.getOpcode() == ISD::AND &&
4454 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
4455 N0.getOperand(1).getOpcode() == ISD::Constant &&
4456 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
4457 N0.getValueType())) {
4458 SDValue X = N0.getOperand(0).getOperand(0);
4464 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4474 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4475 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4476 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
4479 if (!N0.hasOneUse())
4480 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
4482 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4486 N0.getValueType(),
4490 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4491 N0.getValueType(), ExtLoad);
4492 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4502 if (N0.getOpcode() == ISD::LOAD &&
4503 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
4504 N0.hasOneUse()) {
4505 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4513 CombineTo(N0.getNode(),
4514 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4515 N0.getValueType(), ExtLoad),
4520 if (N0.getOpcode() == ISD::SETCC) {
4524 EVT N0VT = N0.getOperand(0).getValueType();
4531 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4532 N0.getOperand(1),
4533 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4545 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4546 N0.getOperand(1),
4547 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4554 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4556 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4607 SDValue N0 = N->getOperand(0);
4623 N0 = SDValue(N, 0);
4624 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1));
4640 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
4641 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
4645 N0 = N0.getOperand(0);
4647 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0)
4652 if (!isa<LoadSDNode>(N0)) return SDValue();
4659 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits())
4667 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
4668 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) {
4669 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
4671 N0 = N0.getOperand(0);
4677 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse() ||
4679 cast<LoadSDNode>(N0)->isVolatile())
4683 if (cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() < EVTBits)
4686 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4687 EVT PtrType = N0.getOperand(1).getValueType();
4706 Load = DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr,
4710 Load = DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(),NewPtr,
4717 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1),
4726 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT,
4735 SDValue N0 = N->getOperand(0);
4743 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
4744 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1);
4747 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1)
4748 return N0;
4751 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
4752 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) {
4754 N0.getOperand(0), N1);
4760 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
4761 SDValue N00 = N0.getOperand(0);
4768 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
4769 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT);
4785 if (N0.getOpcode() == ISD::SRL) {
4786 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
4790 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
4793 N0.getOperand(0), N0.getOperand(1));
4798 if (ISD::isEXTLoad(N0.getNode()) &&
4799 ISD::isUNINDEXEDLoad(N0.getNode()) &&
4800 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
4801 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4803 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4811 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
4815 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
4816 N0.hasOneUse() &&
4817 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
4818 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4820 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4828 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
4833 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) {
4834 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
4835 N0.getOperand(1), false);
4845 SDValue N0 = N->getOperand(0);
4849 if (N0.getValueType() == N->getValueType(0))
4850 return N0;
4852 if (isa<ConstantSDNode>(N0))
4853 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0);
4855 if (N0.getOpcode() == ISD::TRUNCATE)
4856 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
4858 if (N0.getOpcode() == ISD::ZERO_EXTEND ||
4859 N0.getOpcode() == ISD::SIGN_EXTEND ||
4860 N0.getOpcode() == ISD::ANY_EXTEND) {
4861 if (N0.getOperand(0).getValueType().bitsLT(VT))
4863 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4864 N0.getOperand(0));
4865 else if (N0.getOperand(0).getValueType().bitsGT(VT))
4867 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
4871 return N0.getOperand(0);
4881 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
4888 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) {
4944 SDValue N0 = N->getOperand(0);
4952 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
4955 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
4956 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
4957 N0.getOperand(i).getOpcode() != ISD::Constant &&
4958 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
4967 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT);
4971 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
4972 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0);
4988 if (N0.getOpcode() == ISD::BITCAST)
4990 N0.getOperand(0));
4994 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
4996 !cast<LoadSDNode>(N0)->isVolatile() &&
4998 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5009 CombineTo(N0.getNode(),
5010 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5011 N0.getValueType(), Load),
5020 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) &&
5021 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) {
5022 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT,
5023 N0.getOperand(0));
5027 if (N0.getOpcode() == ISD::FNEG)
5030 assert(N0.getOpcode() == ISD::FABS);
5039 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
5040 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
5042 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
5045 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5046 IntXVT, N0.getOperand(1));
5070 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5071 VT, N0.getOperand(0));
5081 if (N0.getOpcode() == ISD::BUILD_PAIR) {
5082 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
5231 SDValue N0 = N->getOperand(0);
5233 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5245 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1);
5248 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0);
5251 return N0;
5254 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0,
5257 if (isNegatibleForFree(N0, LegalOperations) == 2)
5259 GetNegatedExpression(N0, DAG, LegalOperations));
5262 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
5263 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
5264 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0),
5266 N0.getOperand(1), N1));
5272 SDValue N0 = N->getOperand(0);
5274 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5286 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1);
5289 return N0;
5299 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0,
5306 SDValue N0 = N->getOperand(0);
5308 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5320 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1);
5323 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0);
5332 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0);
5336 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0);
5339 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
5345 GetNegatedExpression(N0, DAG, LegalOperations),
5351 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
5352 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
5353 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0),
5355 N0.getOperand(1), N1));
5361 SDValue N0 = N->getOperand(0);
5363 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5375 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1);
5379 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
5385 GetNegatedExpression(N0, DAG, LegalOperations),
5394 SDValue N0 = N->getOperand(0);
5396 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5402 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1);
5408 SDValue N0 = N->getOperand(0);
5410 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5415 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1);
5423 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
5427 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0));
5434 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
5435 N0.getOpcode() == ISD::FCOPYSIGN)
5437 N0.getOperand(0), N1);
5441 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
5446 N0, N1.getOperand(1));
5452 N0, N1.getOperand(0));
5458 SDValue N0 = N->getOperand(0);
5459 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
5461 EVT OpVT = N0.getValueType();
5468 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
5475 if (DAG.SignBitIsZero(N0))
5476 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
5483 SDValue N0 = N->getOperand(0);
5484 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
5486 EVT OpVT = N0.getValueType();
5493 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
5500 if (DAG.SignBitIsZero(N0))
5501 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
5508 SDValue N0 = N->getOperand(0);
5509 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5514 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0);
5520 SDValue N0 = N->getOperand(0);
5521 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5526 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0);
5532 SDValue N0 = N->getOperand(0);
5534 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5538 if (N0CFP && N0.getValueType() != MVT::ppcf128)
5539 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1);
5542 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
5543 return N0.getOperand(0);
5546 if (N0.getOpcode() == ISD::FP_ROUND) {
5549 N0.getNode()->getConstantOperandVal(1) == 1;
5550 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0),
5555 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
5556 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT,
5557 N0.getOperand(0), N1);
5560 Tmp, N0.getOperand(1));
5567 SDValue N0 = N->getOperand(0);
5570 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5582 SDValue N0 = N->getOperand(0);
5583 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5593 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0);
5597 if (N0.getOpcode() == ISD::FP_ROUND
5598 && N0.getNode()->getConstantOperandVal(1) == 1) {
5599 SDValue In = N0.getOperand(0);
5603 In, N0.getOperand(1));
5608 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
5609 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5610 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
5611 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5615 N0.getValueType(),
5619 CombineTo(N0.getNode(),
5620 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(),
5621 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)),
5630 SDValue N0 = N->getOperand(0);
5633 if (isNegatibleForFree(N0, LegalOperations))
5634 return GetNegatedExpression(N0, DAG, LegalOperations);
5638 if (N0.getOpcode() == ISD::BITCAST &&
5640 N0.getNode()->hasOneUse() &&
5641 N0.getOperand(0).getValueType().isInteger()) {
5642 SDValue Int = N0.getOperand(0);
5645 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int,
5657 SDValue N0 = N->getOperand(0);
5658 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5663 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
5665 if (N0.getOpcode() == ISD::FABS)
5669 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
5670 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0));
5674 if (N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() &&
5675 N0.getOperand(0).getValueType().isInteger() &&
5676 !N0.getOperand(0).getValueType().isVector()) {
5677 SDValue Int = N0.getOperand(0);
5680 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int,
6432 SDValue N0 = Value.getOperand(0);
6433 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
6434 Chain == SDValue(N0.getNode(), 1)) {
6435 LoadSDNode *LD = cast<LoadSDNode>(N0);
6485 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(),
6501 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1),
7070 SDValue N0 = N->getOperand(0);
7072 assert(N0.getValueType().getVectorNumElements() == NumElts &&
7081 SDNode *V = N0.getNode();
7106 return N0;
7115 return N0;
7295 SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0,
7297 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
7299 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
7300 cast<CondCodeSDNode>(N0.getOperand(2))->get());
7309 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(),
7310 N0.getValueType(),
7432 /// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3
7434 SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
7446 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
7447 N0, N1, CC, DL, false);
7464 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
7466 return DAG.getNode(ISD::FABS, DL, VT, N0);
7470 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
7512 TLI.getSetCCResultType(N0.getValueType()),
7513 N0, N1, CC);
7531 N0.getValueType().isInteger() &&
7534 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
7535 EVT XType = N0.getValueType();
7544 getShiftAmountTy(N0.getValueType()));
7545 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(),
7546 XType, N0, ShCt);
7557 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(),
7558 XType, N0,
7560 getShiftAmountTy(N0.getValueType())));
7578 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
7579 N0->getValueType(0) == VT &&
7582 SDValue AndLHS = N0->getOperand(0);
7583 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1));
7590 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt);
7597 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt);
7605 TLI.getBooleanContents(N0.getValueType().isVector()) ==
7619 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()),
7620 N0, N1, CC);
7627 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC);
7648 EVT XType = N0.getValueType();
7651 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC);
7661 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0);
7668 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(),
7669 XType, DAG.getConstant(0, XType), N0);
7670 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType);
7678 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0,
7680 getShiftAmountTy(N0.getValueType())));
7695 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1))
7699 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1))
7702 EVT XType = N0.getValueType();
7704 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType,
7705 N0,
7707 getShiftAmountTy(N0.getValueType())));
7708 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(),
7709 XType, N0, Shift);
7720 SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0,
7725 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
