Lines Matching full:i64
351 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
733 if (TLI.isTypeLegal(MVT::i64)) {
735 zextOrTrunc(64), MVT::i64);
2156 case MVT::i64: LC = Call_I64; break;
2171 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2216 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2335 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2338 // Implementation of unsigned i64 to f64 following the algorithm in
2343 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2345 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64);
2349 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64);
2352 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2353 DAG.getConstant(32, MVT::i64));
2354 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2355 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2363 // Implementation of unsigned i64 to f32.
2365 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2373 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2374 SDValue AndConst = DAG.getConstant(1, MVT::i64);
2375 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2376 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2385 SDValue SignBitTest = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2386 Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT);
2392 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2393 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64));
2394 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2395 DAG.getConstant(UINT64_C(0x800), MVT::i64));
2396 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2397 DAG.getConstant(UINT64_C(0x7ff), MVT::i64));
2398 SDValue Ne = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2399 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE);
2400 SDValue Sel = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ne, Or, Op0);
2401 SDValue Ge = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2402 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64),
2404 SDValue Sel2 = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ge, Sel, Op0);
2407 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2439 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2570 case MVT::i64:
2712 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
2721 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
2730 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
2739 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
2748 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
2757 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
2766 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
2775 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
3457 else if (WideVT == MVT::i64)
